11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes

Dong, Qing; Kim, Yejoong; Lee, Inhee; Choi, Myungjoon; Li, Ziyun; Wang, Jingcheng; Yang, Kaiyuan; Chen, Yen‐Po; Dong, Junjie; Cho, Minchang; Kim, Gyouho; Chang, Wei‐Jen; Chen, Yunsheng; Chih, Yu-Der; Blaauw, David; Sylvester, Dennis

doi:10.1109/isscc.2017.7870329

Cited by 17 publications

(15 citation statements)

References 3 publications

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“…the split-gate embedded Flash memory requires 2.8 V voltage for read operation, 8 V voltage supply for program operation and 12 V for erase operation [1,2,3]. However, the area and power of eNVMs are mainly consumed by internal charge pump system [4,5,6]. And the needs of small chip area and ultra-low power eNVMs, which increases battery lifetime and reduces the cost, have become the key design aspects for portable equipment and internet-of-things (IoT) [7,8,9].…”

Section: Introductionmentioning

confidence: 99%

“…As a result, the advanced pump structures with smaller size and higher efficiency have been extensively researched [10,11,12,13,14,15,16,17,18,19]. Meanwhile more attentions are paid to the regulation techniques [20,21,22,23,24,25] or the clock inputs [26,27,28,29,30,31] of charge pumps, since the regulation and clocking schemes have also become more and more crucial to reduce power and chip size of pump system [4,22].…”

Section: Introductionmentioning

confidence: 99%

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A charge pump system with new regulation and clocking scheme

Zhu

Jiang

Lin

et al. 2019

IEICE Electron. Express

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A novel charge pump system with new regulation and clock generating techniques is proposed and verified in a 0.13 µm CMOS process. Rather than generating the reference voltage by band-gap reference (BGR) and the detected voltage by high voltage divider in the conventional regulation, both voltage reference and division of proposed pump system are implemented by single new circuit. Besides, the conventional oscillator for clock input of charge pump system is removed while an adaptive clock generation scheme is introduced to reduce the power consumption and shrink the system size. The experiment results show that the pump system can produce a stable and smooth output with a small ripple, and the high output accuracy is comparable to the conventional solution equipped with BGR. Moreover, the power consumption of the pump controlling is reduced by about 80% while the size of pump system is decreased by about 25%. Therefore, the proposed regulated charge pump (RCP) is very suitable for ultra-low power and high precision applications, for example, the embedded nonvolatile memories (eNVMs).

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A charge pump system with new regulation and clocking scheme

Zhu

Jiang

Lin

et al. 2019

IEICE Electron. Express

View full text Add to dashboard Cite

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“…The t PRE can be effectively reduced by adopting precharge acceleration and dynamic clamping schemes. Also, the double sensing margin and positive feedback of this OC-CSA are realised by M3-M6 (only four transistors), which can lead to the higher area efficiency and lower parasitics, compared with other OC-CSAs with additional capacitors and more transistors (six transistors) [5,6]. Thus, t AMP is also reduced with the lower parasitic capacitance on SA1 and SA2.…”

mentioning

confidence: 98%

“…Rather than voltage-mode sense amplifiers, current-mode SAs (CSAs) are commonly employed by eFlash memory to achieve fast-read performance [3]. Moreover, the differential offset-cancelling CSAs (OC-CSAs), equipped with a double sensing margin technique to further accelerate the sensing speed, have become more and more popular recently [4][5][6]. However, these SAs require extra transistors and capacitors to achieve a double sensing margin, which leads to the additional cost of SA area and deteriorates the sensing performance.…”

mentioning

confidence: 99%

“…F P P P P P P P P F F P P P P P P P F F P P P P P P P F F P P P P P P P F F F P P P P P P F F F P P P P P P F F F P P P P P P F F F F P P P P P F F F F P P P P P F F F F F F P P P Table 1 presents the comparison of simulated read speed among the proposed design, Chang's work [4], Na's work [5] and Dong's work [6]. All of these OC-CSAs are simulated with the 1 Mb eFlash memory under the same conditions (room temperature, typical corner and 1.5 V supply voltage).…”

mentioning

confidence: 99%

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Offset‐cancelling current‐mode sense amplifier for fast‐read eFlash memory

et al. 2019

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A novel offset-cancelling current-mode sense amplifier (OC-CSA) to improve the sensing speed of embedded flash (eFlash) memory is proposed. To reduce the precharge time related to random address transitions, this OC-CSA adopts a new precharge acceleration scheme. Moreover, by employing offset cancellation, double sensing margin and strong positive feedback techniques, the new OC-CSA can achieve a sensing speed 1.6 × faster than other OC-CSAs. A 130 nm 1 Mb eFlash macro to confirm the high-speed capability of the proposed OC-CSA is fabricated. The experiment results show the new OC-CSA can achieve a read access time of 11 ns at VDD = 1.3 V.

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