11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors

Kim, Hyeon‐June

doi:10.1109/jssc.2021.3059909

Cited by 54 publications

(17 citation statements)

References 19 publications

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“…The overall architecture of a CIS specifically includes a pixel array, a row driving module, a column biasing module, a readout circuit, a control circuit, a clock generator, a ramp generator, and a few driving circuits [ 15 , 16 ]. Figure 1 shows the overall architecture of the CIS, in which the pixel array completes the photoelectric signal conversion.…”

Section: Cis System Architecturementioning

confidence: 99%

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

Guo

Wang

2023

Sensors

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The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/−0.6 LSB, and integral nonlinearity (INL) of +1.2/−1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

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Section: Cis System Architecturementioning

confidence: 99%

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

Guo

Wang

2023

Sensors

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“…When the pixel signal decreases according to its own light intensity, it causes fluctuations through the globally shared biasing lines V BIAS1 and V rBIAS2 in the adjacent columns (i.e., coupling noise). Thus, the column bias sampling (CBS) technique [23], [24] is adopted to alleviate the effects of coupling noise. In this study, the LBC scheme is proposed to minimize the power consumption of each column during the T CO period while reducing the bias currents of the pixel SFs.…”

Section: Proposed Readout Schemementioning

confidence: 99%

“…7(a). To alleviate pixel fixed-pattern noise (FPN), optical black pixels (OBPs) [24] are designed and placed on each side of the pixel array, as shown in Fig. 7(b).…”

Section: Circuit Implementationmentioning

confidence: 99%

A Low-Power CMOS Image Sensor With Multiple-Column-Parallel Readout Structure

Hyeon

Kim

2022

IEEE J. Electron Devices Soc.

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This paper presents a low-power multiple-column-parallel (MCP) readout CMOS image sensor (CIS) in terms of its structural features. Because each column in an MCP unit performs analogto-digital (A/D) conversion sequentially, the columns have their own operating periods before and after A/D conversion. Upon completion of A/D conversion in each column, a local bias control (LBC) scheme is applied using a bias circuit of a pixel source follower (SF) to minimize power consumption. In this study, the effectiveness of the proposed LBC scheme is verified for the MCP readout structure. Through simple modification of a column-biasing circuit, the prototype MCP readout CIS achieved significant power savings, which shows its applicability to low-power CIS applications. The prototype CIS was implemented using a 1P6M 0.18-µm CMOS process. A maximum frame rate of 430 fps was achieved while consuming 2.38 mW of power. Compared to a conventional column driver, the proposed LBC scheme reduces the total power consumption by 29.4%, which is an overall power savings of 15%. The prototype CIS also demonstrated figures of merit of 119.1 µV•nJ and 8 µV rms /kHz. INDEX TERMS CMOS image sensor (CIS), pixel source follower, column driver, bias voltage control technique, local bias control (LBC) scheme, multiple-column-parallel (MCP) readout.JANG-SU HYEON (Student Member, IEEE) received the B.S. degree from the

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“…For this reason, the column-parallel structure has mostly been used to design image sensors. [3][4][5] Image sensors consist of two major blocks: pixel signal readout circuit and analog to digital converter (ADC). In recent years, a great number of research studies have been carried out to optimize the efficiency of these two parts.…”

Section: Introductionmentioning

confidence: 99%

“…Depending on the way of reading the pixel signal, there are three conventional architectures for CMOS image sensors: serial, column parallel, and pixel parallel, among which column‐parallel architecture has the most optimal situation regarding power consumption and silicon area. For this reason, the column‐parallel structure has mostly been used to design image sensors 3–5 …”

Section: Introductionmentioning

confidence: 99%

A 256 × 256 CMOS image sensor with differential readout and data converter circuits

Karamzadeh

Teymouri

Dousti

et al. 2023

Circuit Theory & Apps

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Summary In this paper, a 256 × 256 CMOS image sensor is introduced in which the pixel signals are read and converted into digital data in a completely differential mode. This technique helps to obtain pixel signals with higher linearity and accuracy compared with conventional methods. Improving the linearity and accuracy of the image sensor has a direct impact on increasing the quality of the generated images. The simulation results of the proposed pixel readout circuit show that the THD, SINAD, SNR, and SFDR are 0.45%, 47 dB, 66 dB, and 46 dB, respectively. The voltage gain of the proposed readout circuit is about 1, causing it to read the photodetector signals more accurately than the conventional methods. A full differential single‐slope ADC with a working frequency of 50 Mhz has the task of converting the pixel signal to 10 bits of digital data. The total power consumption of a column of sensors is about 80 μW. All the circuits are designed and implemented using 0.18‐μm CMOS technology in Virtuoso and simulated by the SPECTRE.

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11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors

Cited by 54 publications

References 19 publications

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

A Low-Power CMOS Image Sensor With Multiple-Column-Parallel Readout Structure

A 256 × 256 CMOS image sensor with differential readout and data converter circuits

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