11b 60 MHz pipelined ADC with inverter-based class AB amplifier in 28 nm CMOS technology

Abstract

An inverter-based class AB amplifier is proposed to design the 11b pipelined analogue-to-digital converter (ADC) in 28 nm CMOS technology. The structure of the proposed amplifier is more concise compared with conventional amplifiers. The amplifier occupies small area, and its quiescent dissipation is only 1.4 mA. This structure is suitable for design in scaled process. The operation of the amplifier is carefully elaborated. The simulation results show: the ADC can achieve 75.3 dB SFDR and 66.8 dB SNDR, while it occupies an area of 0.4 mm 2 and consumes a power of 17 mW with 1.05 V supply. These results yield a FOMS of 159.3 dB.

A 10-bit 120MS/s SAR ADC using tri-switch sampling and VCM-stable switching scheme in 40-nm CMOS

“…Over the course of several decades, some ADC architectures have been developed and widely used, such as flash [1,2,3], pipeline [4,5,6], sigma-delta [7,8], SAR [9,10,11,12], and interleaved [13,14,15] ADCs. Each owns specific characteristics in terms of sample rate, accuracy, etc.…”