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A set of behavioral voltage-domain verilogA/ verilog models is proposed in the paper, based on mathematical models of building blocks and some simulation strategies. The models include nonlinear effects of building blocks and can accurately predict the dynamic or stable characteristic of the closed loop. A three-order RD fractional-N PLL based frequency synthesizer with a 1.9 GHz central output frequency is implemented with the presented way. Cadence SpectreVerilog simulation results show that the behavioral modeling can provide a great speed-up over the transistor-level simulation. Correspondingly, the phase noise, spurious tones and loop locked time can also be accurately predicted, so it is helpful to optimization design based on system-level.

In this article, we proposed an analytical model based on charge distribution for switched-capacitor trans-impedance amplifiers (SCTIAs). The changes in the load state of the amplifier under different operating conditions and the influence of the gain of the operational amplifier (Opamp) on the trans-impedance gain are analyzed to improve the design theory of switched-capacitor trans-impedance amplifiers. According to the conclusion drawn from the analysis, the trans-impedance amplifier (TIA) has been designed by adopting “correlated double sampling technology” and “cross-connection technology” to optimize input-referred noise current, power consumption, and trans-impedance gain. As a result, the trans-impedance gain reaches up to 206 dB, while the bandwidth is 3 kHz. The current readout system achieves an input-referred noise current floor of 2.96 fA/Hz at 1 kHz, and the power consumption of the system is 0.643 mW. The circuit has been simulated with the technology of 0.18 μm, and the layout area is 1000 μm × 500 μm.

A novel process-insensitive thermal protection structure has been developed. This circuit contains several sub-circuits such as band-gap reference, reference output buffer, resistance voltage divider branch, and hysteresis circuit. By using reference buffer, the precise reference voltage from band-gap reference is delivered to resistance voltage divider branch and is divided precisely. Then the threshold temperatures of this protection circuit can be set by this precise voltage, unaffected by process variation and mismatch. A hysteresis circuit is also used here to prevent thermal oscillation. This circuit is fabricated in TSMC 0.18 m CMOS technology, and occupies about 3 10 4 m 2 chip area.