Modeling and Simulation to the Design of EA Fractional-N Frequency Synthesizer

Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS

“…For comparison, two other conventional models were also used to model the analog block depicted in Fig. 15 within a shadowed box, i.e., the SPICE model using Verilog-AMS with analog nets [12] and a modified version of an event-based forward Euler [25]. All other blocks of the PLL are modeled in the same way using Verilog.…”

A Precise and High Speed Charge-Pump PLL Model Based on SystemC/SystemC-AMS

“…However, when designing a PLL, one of the main problems is that the closed loop simulation of a PLL is very time consuming, especially at transistor level. For example, a fine frequency resolution required in noise simulation often leads to an over 24-hour simulation time [1]. Therefore, to examine the closed loop behavior, a fast and precise model is highly desirable.…”

“…Many efforts have been spent to address this problem, such as in [1] and [2] where Verilog-AMS models are presented. However, these models have their limitations in terms of simulation performance.…”

“…However, these models have their limitations in terms of simulation performance. For instance, in [1], the high frequency output of the Voltage Control Oscillator (VCO) is not generated in order to reduce simulation time. But in this way, it is impossible to insert the PLL into a radio system model for further testing.…”

Cell based synthesized low noise all digital frequency synthesizer, 0.13μm CMOS and FPGA implementations

“…Adding a EA modulator into the simulation code will make it possible to study the EA modulator phase noise effect. Reference[31] does this by a different mixed signal simulator SpectreVerilog from Cadence. With the advance of the CMOS process, more and more circuit components can be integrated into a single chip and most SoC designs have one or more PLL blocks.…”