12.1 A rational-conversion-ratio switched-capacitor DC-DC converter using negative-output feedback

Jung, Wanyeong; Sylvester, Dennis; Blaauw, David

doi:10.1109/isscc.2016.7417985

Cited by 42 publications

(15 citation statements)

References 3 publications

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“…The step-up architecture based on voltage doubler (VD) is conducted. This design is inspired by the ideas in step-down charge pump [7][8][9], in which several basic modules are connected in series to form more VCRs. As shown in Figure 2, when we make several VD units cascade together and set the dynamic voltage in each VD unit dexterously, an arbitrary integer VCR can be obtained, and the output voltage for the n-stage topology is given by…”

Section: Basic Topology Of the Highly Integrated Charge Pumpmentioning

confidence: 99%

“…In this way, a higher frequency means less voltage loss during charging, higher current drivability and faster transient response for charge pump system. This multi-phase solution is also suitable for the step-down charge pump topologies, such as [7][8][9], to optimize its operation frequency and total performance. But for the step-up converter shown above, it is a rather critical scheme since the high-voltage transistor has poor current-drive-capacity and then the power converter has high RC time constant for each charging chain.…”

Section: Basic Topology Of Multi-phase Charge Pumpmentioning

confidence: 99%

See 1 more Smart Citation

P‐45: A Multi‐Phase, High‐Current‐Drivability Charge Pump in Display Driver ICs

Lin

Ding

Liu

et al. 2018

Symp Digest of Tech Papers

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In this work, a multi-phase charge pump topology is proposed to drive the display driver integrated circuits. To achieve high integration and power efficiency simultaneously, a converter with full-coverage voltage conversion ratios ranging from 1 to 2 n is realized while the count of off-chip capacitors is halved. At the same time, the charging period for each clock phase is designed to be equal and it allows a higher operation frequency of 2 n /(n+1) times while the capacitor can still be fully charged. Based on 0.25 μm process, a three-stage topology has been performed. It has improved the current drivability by 40%-150%. This design is quite suitable for display panels with higher resolution requirements. Author KeywordsMulti-phase charge pump; voltage conversion ratio; charging period; current drivability; display driver. P-45 /H. Lin • SID 2018 DIGEST

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Section: Basic Topology Of the Highly Integrated Charge Pumpmentioning

confidence: 99%

Section: Basic Topology Of Multi-phase Charge Pumpmentioning

confidence: 99%

P‐45: A Multi‐Phase, High‐Current‐Drivability Charge Pump in Display Driver ICs

Lin

Ding

Liu

et al. 2018

Symp Digest of Tech Papers

View full text Add to dashboard Cite

show abstract

“…Combining all these losses together, one can describe the total loss of a SC converter as P loss = P SSL + P F SL + P BP + P trans + P l . (12) Note that while the total conduction losses (combination of P SSL and P F SL ) can be more accurately formulated using either a quadratic sum [15] or variations thereof [21], the addition used here allows us to simplify the equations and still come up with insightful conclusions, similar to the approach in [7]. Also, rather than optimizing P loss , the normalized losses P N = P loss P L , with P L the load power, are used.…”

Section: Regular Sc Optimizationmentioning

confidence: 99%

“…The highest reported fully integrated closed-loop converter efficiencies in baseline CMOS are 87% [10], although at a more favorable VCR of 2/3, and 85% [11], both using MIM capacitors. Higher efficiencies have been demonstrated using either openloop converters with VCR's very close to 1:1 (95% in 15/16) [12], or high-density Deep-Trench (88% in 1/2) [13] or Ferro-Electric (91% in 1/2) [14] capacitors, which have reportedly up to 25 times lower α BP . However, these capacitors are not part of baseline CMOS and thus require additional masks and costs.…”

Section: Introductionmentioning

confidence: 99%

Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC–DC Converters

Butzen

Steyaert

2016

IEEE J. Solid-State Circuits

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This paper introduces a technique, called Scalable Parasitic Charge Redistribution (SPCR), that reduces the parasitic Bottom-Plate (BP) losses in fully-integrated Switched-Capacitor (SC) voltage regulators up to any desired level. This is realized by continuously redistributing parasitic charge in-between phase-shifted converter cores. Because earlier models described the ratio of this parasitic coupling to the flying capacitance as the only limiting factor on the achievable fully-integrated efficiency, the use of SPCR allows SC converters to achieve efficiencies previously deemed impossible. Transistor leakage is shown to be another limiting factor and is added to existing models which are then used to prove the effectiveness of SPCR over a wide range of power densities (up to 10W/mm 2) and technological parameters. The implementation of SPCR requires little overhead thanks to the use of Charge Redistribution Buses. A 1/2 converter is fabricated in a 40nm bulk CMOS technology that demonstrates SPCR by achieving a record efficiency for fully-integrated closed-loop SC converters of 94.6%.

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“…For example, a 2:1 SC DC-DC converter shows high efficiency at only the output voltage of half of the input voltage. To overcome it, reconfigurable SC topologies which support many conversion ratios were presented [8,9]. The reconfigurable SC can provide the wide-range input and output by adjusting conversion ratios based on the input voltage and required output voltage.…”

Section: Introductionmentioning

confidence: 99%

Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

Choi

Jeong

2020

Electronics

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A soft-switching hybrid DC-DC converter with a 2-phase switched capacitor is proposed for the implementation of a fully-integrated voltage regulator in a 65 nm standard CMOS process. The soft-switching operation is implemented to minimize power loss due to the parasitic capacitance of the flying capacitor. The 2-phase switched capacitor topology keeps the same resonance value for every soft-switching operation, resulting in minimizing the voltage imbalance of the flying capacitor. The proposed adaptive timing generator digitally calibrates the turn-on delay of switches to achieve a complete soft-switching operation. The simulation results show that the proposed soft-switching hybrid DC-DC converter with a 2-phase 2:1 switched capacitor improves the efficiency by 5.1% and achieves 79.5% peak efficiency at a maximum load current of 250 mA.

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12.1 A rational-conversion-ratio switched-capacitor DC-DC converter using negative-output feedback

Cited by 42 publications

References 3 publications

P‐45: A Multi‐Phase, High‐Current‐Drivability Charge Pump in Display Driver ICs

P‐45: A Multi‐Phase, High‐Current‐Drivability Charge Pump in Display Driver ICs

Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC–DC Converters

Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

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