12.2 A 94.6%-efficiency fully integrated switched-capacitor DC-DC converter in baseline 40nm CMOS using scalable parasitic charge redistribution

Butzen, Nicolas; Steyaert, Michiel

doi:10.1109/isscc.2016.7417986

Cited by 42 publications

(24 citation statements)

References 6 publications

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“…Among the capacitors in a standard CMOS process, the MOS capacitor generally shows a high capacitance density of 4 nF/mm 2 up to 12 nF/mm 2 while it has a bottom-plate parasitic capacitance of around 10%. Although MIM and MOM capacitors have lower parasitic capacitances of around 1.5%, these show lower capacitance densities of up to 2 nF/mm 2 [6,15]. For example, if a 2 nF flying capacitor with a 5% parasitic capacitance is implemented for the FIVR, the power loss due to C par can be tens of milliwatts.…”

Section: Proposed Soft-switching Hybrid Dc-dc Convertermentioning

confidence: 99%

“…For example, if a 2 nF flying capacitor with a 5% parasitic capacitance is implemented for the FIVR, the power loss due to C par can be tens of milliwatts. To overcome it, the SC DC-DC converter shown in [15] proposed the scalable parasitic charge redistribution technique with multi-phase SCs. By redistributing the charge of the parasitic capacitor to another flying capacitor of the opposite-phase SC instead of discharging to ground, it can improve the power efficiency of the converter implemented in a standard CMOS process.…”

Section: Proposed Soft-switching Hybrid Dc-dc Convertermentioning

confidence: 99%

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Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

Choi

Jeong

2020

Electronics

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A soft-switching hybrid DC-DC converter with a 2-phase switched capacitor is proposed for the implementation of a fully-integrated voltage regulator in a 65 nm standard CMOS process. The soft-switching operation is implemented to minimize power loss due to the parasitic capacitance of the flying capacitor. The 2-phase switched capacitor topology keeps the same resonance value for every soft-switching operation, resulting in minimizing the voltage imbalance of the flying capacitor. The proposed adaptive timing generator digitally calibrates the turn-on delay of switches to achieve a complete soft-switching operation. The simulation results show that the proposed soft-switching hybrid DC-DC converter with a 2-phase 2:1 switched capacitor improves the efficiency by 5.1% and achieves 79.5% peak efficiency at a maximum load current of 250 mA.

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Section: Proposed Soft-switching Hybrid Dc-dc Convertermentioning

confidence: 99%

Section: Proposed Soft-switching Hybrid Dc-dc Convertermentioning

confidence: 99%

Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

Choi

Jeong

2020

Electronics

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“…As such, one can argue that the parasitic capacitor is exchanging charge with a time-shifted version of itself. By splitting the parasitic capacitor up into multiple phase-shifted versions of itself, each phase can at each point in time connect to another that goes through the opposite voltage step [14], as shown in Fig. 5, and the middleman can be cut.…”

Section: Working Principlementioning

confidence: 99%

“…In [14] a technique called Scalable Parasitic Charge Redistribution (SPCR) is introduced that significantly increases the efficiency of SC converters by redistributing charge between parasitic capacitors. Exploring the SPCR technique, a series of DC voltage levels that are evenly spread across the flying capacitors' Bottom-Plate (BP) swing can easily be implemented.…”

Section: Introductionmentioning

confidence: 99%

MIMO Switched-Capacitor DC–DC Converters Using Only Parasitic Capacitances Through Scalable Parasitic Charge Redistribution

Butzen

Steyaert

2017

IEEE J. Solid-State Circuits

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“…Finally, this work is compared to the state-of-the-art of fully-integrated closed-loop SC converters in Fig. 18 and Table III [24]. Thanks to the presented Scalable Parasitic Charge Redistribution (SPCR) technique, the realized converter achieves a higher efficiency than any other fully-integrated SC regulator, including those using Deep-Trench and Ferro-Electric capacitors which require extra masks.…”

Section: Comparisonmentioning

confidence: 99%

Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC–DC Converters

Butzen

Steyaert

2016

IEEE J. Solid-State Circuits

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This paper introduces a technique, called Scalable Parasitic Charge Redistribution (SPCR), that reduces the parasitic Bottom-Plate (BP) losses in fully-integrated Switched-Capacitor (SC) voltage regulators up to any desired level. This is realized by continuously redistributing parasitic charge in-between phase-shifted converter cores. Because earlier models described the ratio of this parasitic coupling to the flying capacitance as the only limiting factor on the achievable fully-integrated efficiency, the use of SPCR allows SC converters to achieve efficiencies previously deemed impossible. Transistor leakage is shown to be another limiting factor and is added to existing models which are then used to prove the effectiveness of SPCR over a wide range of power densities (up to 10W/mm 2) and technological parameters. The implementation of SPCR requires little overhead thanks to the use of Charge Redistribution Buses. A 1/2 converter is fabricated in a 40nm bulk CMOS technology that demonstrates SPCR by achieving a record efficiency for fully-integrated closed-loop SC converters of 94.6%.

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12.2 A 94.6%-efficiency fully integrated switched-capacitor DC-DC converter in baseline 40nm CMOS using scalable parasitic charge redistribution

Cited by 42 publications

References 6 publications

Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

MIMO Switched-Capacitor DC–DC Converters Using Only Parasitic Capacitances Through Scalable Parasitic Charge Redistribution

Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC–DC Converters

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