120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board

B, Chethan Kumar H; Ravi, P Gupta; Modi, Gourav; Kapre, Nachiket

doi:10.1145/3020078.3021751

Cited by 13 publications

(5 citation statements)

References 8 publications

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“…The synchronous version offers slightly better performance as it has fewer software overheads, but it will be interesting to monitor this comparison in future as the size of our cluster grows and the cost of global synchronisation increases. [24] which adapts an existing 32-bit MIPS core (from the Imagination Technologies Academic Program) for the DE5-Net FPGA, and adds support for lightweight intercore messaging over a Hoplite NoC [25]. A side-by-side comparison against Tinsel is shown in Figure 13.…”

Section: Methodsmentioning

confidence: 99%

See 1 more Smart Citation

Tinsel: A Manythread Overlay for FPGA Clusters

Naylor

Moore

Thomas

2019

2019 29th International Conference on Field Programmable Logic and Applications (FPL)

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Commodity FPGA boards with advanced networking facilities have great potential in the construction of highperformance compute clusters that scale. However, low-level design tools and long synthesis times are major barriers to productivity for application developers. In this paper, we explore the potential of a distributed soft-processor overlay, programmed in software at a high-level of abstraction, to deliver a useful level of performance for FPGA clusters. In particular, we demonstrate the use of hardware multhreading to achieve a fast, spaceefficient, high-throughput overlay, and compare a 12-FPGA instance of it (12,288 RISC-V threads) against a conventional Xeon cluster on the problem of distributed graph processing.

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Section: Methodsmentioning

confidence: 99%

“…13. Feature set of the Tinsel overlay versus the µaptive overlay[24], including clock frequencies and area requirements on the DE5-Net board.…”

mentioning

confidence: 99%

Tinsel: A Manythread Overlay for FPGA Clusters

Naylor

Moore

Thomas

2019

2019 29th International Conference on Field Programmable Logic and Applications (FPL)

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“…In addition, if the final chip is looked at under a microscope, one can hardly see the original fine-grained structure. And if we talk about the implementation of a NoC on an FPGA chip (which has already reached such sizes that it can fit a network of tens and hundreds of nodes [20]), then it is even more difficult to maintain the initial abstraction in it with the representation of individual macroblocks in the form of rectangles due to uneven distribution of chip resources on the FPGA die area. Also, the simplification that the main connection routes between routers pass between macroblocks does not correspond to reality because the chip is initially multilayered, and the connections go through several metal layers.…”

Section: Topological Approachmentioning

confidence: 99%

Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip

Sukhov,

Romanov,

Selin

2024

Symmetry

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In this work, the circulant topology as an alternative to 2D mesh in networks-on-chip is considered. A virtual coordinate system for numbering nodes in the circulant topology is proposed, and the principle of greedy promotion is formulated. The rules for constructing the shortest routes between the two nodes based on coordinates are formulated. A technique for calculating optimal network configurations is described. Dense states of the network when all neighborhoods of the central node are filled with nodes and the network has the smallest diameter are defined. It is shown that with an equal number of nodes, the diameter of the circulant is two times smaller than the diameter of the 2D mesh. This is due to the large number of symmetries for the circulant, which leave the set of nodes unchanged. A comparison of communication stability in both topologies in the conditions of failure of network nodes is made, the network behavior under load and failures is modeled, and the advantages of the circulant topology are presented.

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“…This type of courses is beyond the initial scope of MIPSfpga but, as we stated previously, lecturers have the freedom to adapt the contents of the Getting Started package to their own needs. As an example, the authors in [22] have engaged in some heavy modifications of the source code of the microAptiv core contained in the MIPSfpga system to develop a 120‐core system that then can be downloaded onto a Terasic DE5‐NET FPGA.…”

Section: Related Workmentioning

confidence: 99%

MIPSfpga: using a commercial MIPS soft‐core in computer architecture education

Harris

Chaver

et al. 2017

IET Circuits, Devices & Systems

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In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal for both the classroom and research. The supporting materials and labs focus on hands-on learning that emphasises computer architecture, system on chip (SoC) design and hardware-software codesign. Among other things, students learn to set up the MIPS soft-core processor on an FPGA, run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.

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120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board

Cited by 13 publications

References 8 publications

Tinsel: A Manythread Overlay for FPGA Clusters

Tinsel: A Manythread Overlay for FPGA Clusters

Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip

MIPSfpga: using a commercial MIPS soft‐core in computer architecture education

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