13.4 A 512Gb 3-bit/Cell 3D 6<sup>th</sup>-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface

Kang, Dong‐Ku; Kim, Minsu; Jeon, Su Chang; Jung, Wontaeck; Park, Jooyong; Choo, Gyosoo; Shim, Dong-Kyo; Kavala, Anil; Kim, Seungbum; Kang, Kyung-Min; Lee, Ji-Young; Ko, Kuihan; Park, Hyun-Wook; Min, Byung-Jun; Yu, Chang Yeon; Yun, Se-Won; Kim, Nahyun; Jung, Yeonwook; Seo, Sungwhan; Kim, Sung Hoon; Lee, Moo Kyung; Park, Joo-Yong; Kim, James C.; San, Young; Kim, Kwangwon; Jo, Youngmin; Kim, Hyun‐Jin; Choi, Yong‐Sang; Byun, Joonho; Park, Jihyun; Kim, Ki-Won; Kwon, Taehong; Min, Young-Sun; Yoon, Chi-Weon; Kim, Young-Cho; Kwak, Donghun; Lee, Eungsuk; Hahn, Wook-Ghee; Kim, Ki-Sung; Kim, Kyungmin; Yoon, Euisang; Kim, Won‐Tae; Lee, Inryoul; Moon, Seung Hyun; Ihm, Jeong-Don; Byeon, Dae Seok; Song, Ki–Whan; Hwang, Sangjoon; Kyung, Kye Hyun

doi:10.1109/isscc.2019.8662493

Cited by 46 publications

(17 citation statements)

References 4 publications

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“…TCAT subsequently evolved into V-NAND architecture, which has 32-stacked word line (WL) layers [26][27][28]. The industry has moved beyond 12x-stacked WL layers and achieved a 17x-stacked V-NAND [29,30]. As the memory industry transitions from planar to 3D scaling, traditional device reliability issues must still be considered.…”

Section: Introductionmentioning

confidence: 99%

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Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Chiu

Shirota

2021

Electronics

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NAND Flash memories have gained tremendous attention owing to the increasing demand for storage capacity. This implies that NAND cells need to scale continuously to maintain the pace of technological evolution. Even though NAND Flash memory technology has evolved from a traditional 2D concept toward a 3D structure, the traditional reliability problems related to the tunnel oxide continue to persist. In this paper, we review several recent techniques for separating the effects of the oxide charge and tunneling current flow on the endurance characteristics, particularly the transconductance reduction (ΔGm,max) statistics. A detailed analysis allows us to obtain a model based on physical measurements that captures the main features of various endurance testing procedures. The investigated phenomena and results could be useful for the development of both conventional and emerging NAND Flash memories.

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Section: Introductionmentioning

confidence: 99%

“…Q CT obtained by fitting experimental data using Equation (5) for different values of T cyc . Reprinted from[29].…”

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confidence: 99%

Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Chiu

Shirota

2021

Electronics

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“…Static RAM (SRAM) [1][2][3][4][5][6][7][8][9][10] and dynamic RAM (DRAM) [11][12][13][14][15][16][17][18][19][20] (conventional volatile memories) suffer from significant leakage power and flash memory [21][22][23][24][25][26][27][28][29][30] (conventional non-volatile memories (NVMs)) suffers from high write power and poor endurance/ performance. However, emerging NVMs can be beneficial since they offer zero leakage and high scalability, density, and endurance [31].…”

Section: Introductionmentioning

confidence: 99%

Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

Khan

Ghosh

2021

JLPEA

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Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues.

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“…To satisfy this demand, NAND flash memory can be a promising candidate for a synaptic device to meet this requirement. NAND flash memory offers ultra-high bit density for immense data storage and low fabrication cost per bit, and it has been well known as a mature technology (Yamashita et al, 2017;Kang et al, 2019;Huh et al, 2020). However, NAND flash memory was not commonly used in neuromorphic system because of the characteristics of the string structure.…”

Section: Introductionmentioning

confidence: 99%

Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme

Lee

2020

Front. Neurosci.

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A novel operation scheme is proposed for high-density and highly robust neuromorphic computing based on NAND flash memory architecture. Analog input is represented with time-encoded input pulse by pulse width modulation (PWM) circuit, and 4-bit synaptic weight is represented with adjustable conductance of NAND cells. Pulse width modulation scheme for analog input value and proposed operation scheme is suitably applicable to the conventional NAND flash architecture to implement a neuromorphic system without additional change of memory architecture. Saturated current-voltage characteristic of NAND cells eliminates the effect of serial resistance of adjacent cells where a pass bias is applied in a synaptic string and IR drop of metal wire resistance. Multiply-accumulate (MAC) operation of 4-bit weight and width-modulated input can be performed in a single input step without additional logic operation. Furthermore, the effect of quantization training (QT) on the classification accuracy is investigated compared with post-training quantization (PTQ) with 4-bit weight. Lastly, a sufficiently low current variance of NAND cells obtained by the read-verify-write (RVW) scheme achieves satisfying accuracies of 98.14 and 89.6% for the MNIST and CIFAR10 images, respectively.

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13.4 A 512Gb 3-bit/Cell 3D 6^th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface

Cited by 46 publications

References 4 publications

Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme

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13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface

Cited by 46 publications

References 4 publications

Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories

Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme

Contact Info

Product

Resources

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13.4 A 512Gb 3-bit/Cell 3D 6^th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface