13-Gb/s Transmitter for Bunch of Wires Chip-to-Chip Interface Standard

Abstract

Continuous downscaling of integrated circuits has reached a bottleneck. Technologies such as system in a package, multi-chip module and integration of chips on an active or passive interposer can further improve the system performance. Bunch of wires interface standard was recently introduced for chip to chip short interfaces within a package. This standard required both terminated and unterminated driver topologies for different data rates and interconnect lengths. This paper presents a first ever reported transmitter implementation of this interface. Unterminated and terminated impedance controlled drivers with feedback calibration enable transmitter power optimization for a given interconnect based on the respective signal integrity at the receiver side. Results show that this transmitter can support both low and high speed low power communication between chips for interconnects up to 11 mm length with energy consumption of 0.34 pJ/bit at maximum data rate of 13 Gb/s. The transmitter is designed and taped out in 22 nm FDSOI technology node.

Holistic Die-to-Die Interface Design Methodology for 2.5-D Multichip-Module Systems

“…For signal transmission over wire, the most popular are current mode logic (CML) differential signalling [31] and source series terminated logic (SSTL) [32]. Both of these topologies assume transmitter termination along with a far end receiver termination for good signal integrity at high data rates.…”

“…The first voltage mode source series termination signalling topology to be studied here, uses GND termination at the receiver end as shown in the Figure 6 [32]. Here, the power source vdd sources current during high bit transmission resulting in voltage v oh at the receiver.…”

“…Here, the power source vdd sources current during high bit transmission resulting in voltage v oh at the receiver. On the other hand, there is no current sourced during the low bit transmission v ol [32]. Hence,…”