Continuous downscaling of integrated circuits has reached a bottleneck. Technologies such as system in a package, multi-chip module and integration of chips on an active or passive interposer can further improve the system performance. Bunch of wires interface standard was recently introduced for chip to chip short interfaces within a package. This standard required both terminated and unterminated driver topologies for different data rates and interconnect lengths. This paper presents a first ever reported transmitter implementation of this interface. Unterminated and terminated impedance controlled drivers with feedback calibration enable transmitter power optimization for a given interconnect based on the respective signal integrity at the receiver side. Results show that this transmitter can support both low and high speed low power communication between chips for interconnects up to 11 mm length with energy consumption of 0.34 pJ/bit at maximum data rate of 13 Gb/s. The transmitter is designed and taped out in 22 nm FDSOI technology node.

In recent years, 2.5D integration of ICs on Interposer is becoming popular for highly integrated miniaturized systems. To combine two or more chips together, there is a lot of communication between the chips and this needs either a very high number of slow channels or numerous high speed channels. To find an optimum number and speed of interposer channels is an important task. In conventional PCB data communication systems, very high speed serial data transmission circuits are used which take a lot of area and power. While in 2.5D systems, area-power are strict constraints and the interposer channel is drastically different from PCB channel in terms of its electrical properties. To enable high bandwidth chip-to-chip interposer communication with low area-power requirements, it is mandatory to co-design the interposer channel and IO circuit. To address the issue, this paper discusses the electrical properties of 2.5D channel segments along with a co-design methodology targeting optimum area-power cost for maximum bandwidth current mode logic differential driver.

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In this presentation we will show different manufacturing approaches for TSVs which results in different shapes and dimensions. For example, geometries for tungsten filled very small TSVs (smaller than 5um) into very thin 2D chips (under 50um thickness) are shown. Also different assembly technologies for the mounting of the different chips to 2.5D and real 3D systems are explained. The usage of such 2.5 or 3D integrated systems in real world examples for high bandwidth processor memory communications are demonstrated

High speed communication has been a topic of great interest in the last decade due to excessively high data rates required between chips especially pushed by the measurement equipment industry to support extremely high bandwidth data sampling. Serial communication is chosen to support these data rates which are pushing further and further into higher data rate regimes. It is important to understand how the 2.5D integration of chips on the interposer can support serial communication and what the designer can do to leverage the special features of interposer channel to achieve lower power and higher speed. This paper will present the interposer complete channel full 3D Electromagnetic simulation based model extraction. It also presents the simulation of channel with real serial communication transmitter and receiver circuit models to describe the proposed interposer performance for multi Gb/s data rates. Also a comparison is shown for different settings of transmitter and receiver circuits under the interposer channel.