Co-design of CML IO and Interposer channel for low area and power signaling

Abstract

In recent years, 2.5D integration of ICs on Interposer is becoming popular for highly integrated miniaturized systems. To combine two or more chips together, there is a lot of communication between the chips and this needs either a very high number of slow channels or numerous high speed channels. To find an optimum number and speed of interposer channels is an important task. In conventional PCB data communication systems, very high speed serial data transmission circuits are used which take a lot of area and power. While in 2.5D systems, area-power are strict constraints and the interposer channel is drastically different from PCB channel in terms of its electrical properties. To enable high bandwidth chip-to-chip interposer communication with low area-power requirements, it is mandatory to co-design the interposer channel and IO circuit. To address the issue, this paper discusses the electrical properties of 2.5D channel segments along with a co-design methodology targeting optimum area-power cost for maximum bandwidth current mode logic differential driver.

Holistic Die-to-Die Interface Design Methodology for 2.5-D Multichip-Module Systems

“…For signal transmission over wire, the most popular are current mode logic (CML) differential signalling [31] and source series terminated logic (SSTL) [32]. Both of these topologies assume transmitter termination along with a far end receiver termination for good signal integrity at high data rates.…”

“…This section uses the holistic energy-pitch minimization methodology to optimize the design of current mode logic (CML) transmitter front end and interposer for optimum energy and area efficiency [31]. Generally, the impedance of the CML drivers is designed as 50 Ω for PCB based systems.…”

“…Based upon the basic transmission line theory, the insertion loss of the differential pair is dependent upon both the conductor R and dielectric G conductance [31].…”