Current and future 3D activities at Fraunhofer

Abstract

In this presentation we will show different manufacturing approaches for TSVs which results in different shapes and dimensions. For example, geometries for tungsten filled very small TSVs (smaller than 5um) into very thin 2D chips (under 50um thickness) are shown. Also different assembly technologies for the mounting of the different chips to 2.5D and real 3D systems are explained. The usage of such 2.5 or 3D integrated systems in real world examples for high bandwidth processor memory communications are demonstrated

Co-design of CML IO and Interposer channel for low area and power signaling

“…In [3], comparison of silicon, glass and organic interposer is presented which shows that silicon substrate interposer has higher attenuation factor as compared to glass and organic ones. In [5], Through silicon via (TSV) options are described along with routing problems for 2.5D integration based processormemory interfaces. In our work, the 2.5D channel is studied along with the co-design of signaling circuit to achieve the Section IV discusses the co-design methodology and algorithm used to find the optimum power area cost.…”