130-GHz On-Chip Meander Slot Antennas With Stacked Dielectric Resonators in Standard CMOS Technology

Abstract

This work discusses the design methodologies of 130-GHz high gain and high efficiency on-chip meander slot antennas in a standard CMOS technology. In the proposed structure, stacked dielectric resonators (DRs) are placed on the top of the on-chip feeding element to form series-fed antenna array for antenna gain and efficiency improvement. The integrated antenna with double stacked DRs achieved a measured gain of 4.7 dBi at 130 GHz with a bandwidth of 11%. The antenna size is and the simulation results indicate a radiation efficiency of 43%. To the best of our knowledge, this is the first demonstration of an on-chip antenna gain and efficiency enhancement through stacked DRs. Index Terms-CMOS, dielectric resonator antenna (DRA), millimetre wave, on-chip antenna, silicon.

D-band on-chip higher-order-mode dielectric-resonator antennas fed by half-mode cavity in CMOS technology

“…The slot-feeding structure without shielded ground [4,19] (type I) showed lower antenna efficiency, which was caused by the substrate losses of the lossy silicon. Compared with the slot dipole with backed cavity fed by coplanar waveguide [5][6][7] (type II), the proposed half-mode cavity feeding structure revealed higher effi ciency with comparable chip area. The smooth fi eld distribution of the halfmode cavity shown in Figure 4 led to a higher Q factor, which benefi ted the effi ciency improvement.…”

“…The adjacent dipoles with opposite direction were separated with a spacing p. The feeding structure could be treated as a ground plane. The normalized far-fi eld electric-fi eld pattern of the equivalent model could be expressed based on the image theory and pattern-multiplication principle [7,10] …”

“…The experiment showed that most of the samples had a glue thickness of between 5 µm and 20 µm. According to the analysis in [7], the achieved thickness value range should have had little affect on the antenna gain (within 0.5 dB deterioration). As to the assembly of the dielectric resonator, some alignment marks were fabricated on the sur face of the chip, shown in Figure 14a, which was benefi cial to the resonator position.…”

“…The application of the dielec tricresonator antenna to silicon-based technology was also verifi ed in [4][5][6], with notable effi ciencies of 40% to 50% and gains of 1 dBi to 3 dBi. Our previous research using stacked dielectricresonator (DR) technology [7] managed to push the antenna gain up to 4.7 dBi. This showed that the on-chip dielectricresonator antenna is a promising technology for improvement of the antenna's performance.…”

“…With the help of these technologies, the peak gain of the on-chip higher-order dielectric-resonator antenna was measured to be 7.5 dBi at 134 GHz, which is a record for all of the on-chip dielectric-resonator-antenna implementations reported so far. Compared with our previous work in [7], we utilized a single higher-order-mode dielectric resonator in this work, rather than multi-dielectric resonators, to achieve higher-gain per formance, even though a narrower impedance bandwidth was produced. This work also simplifi ed the antenna assembly processes, and was good for reducing cost.…”