This work discusses the design methodologies of 130-GHz high gain and high efficiency on-chip meander slot antennas in a standard CMOS technology. In the proposed structure, stacked dielectric resonators (DRs) are placed on the top of the on-chip feeding element to form series-fed antenna array for antenna gain and efficiency improvement. The integrated antenna with double stacked DRs achieved a measured gain of 4.7 dBi at 130 GHz with a bandwidth of 11%. The antenna size is and the simulation results indicate a radiation efficiency of 43%. To the best of our knowledge, this is the first demonstration of an on-chip antenna gain and efficiency enhancement through stacked DRs. Index Terms-CMOS, dielectric resonator antenna (DRA), millimetre wave, on-chip antenna, silicon.

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In this paper, on-chip higher-order-mode dielectric-resonator antennas (DRAs), fed by a half-mode-backed cavity structure using standard CMOS technology, are presented. With the dominant cavity mode (half-100 z TE ), the half-mode cavity-feeding structure provided a high antenna radiation effi ciency. The dielectric resonators (DRs) were designed to operate at higher-order modes ( 13 x δ TE , 15 x δ TE ) to enhance the antenna gain. At around 135 GHz, the proposed antennas demonstrated measured gains of 6.2 dBi and 7.5 dBi for the 13 x δ TE and 15 x δ TEmodes, respectively, with corresponding simulated radiation effi ciencies of 46% and 42%. Both antennas had a measured impedance bandwidth of 7%. The proposed antennas not only accomplished high gain without occupying a large chip area, but also maintained comparable or even improved cost performance and simplicity over other on-chip antennas.

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