130nm Low power asynchronous AES core

El-Meligy, Nada E.; Amin, Moustafa; Yahya, E.; Ismail, Yehea

doi:10.1109/iscas.2017.8050832

Cited by 9 publications

(4 citation statements)

References 5 publications

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“…Hence, the 128-bit architectures mentioned in [17], [18], [19] are not suitable for the implementation in constrained devices due to power requirements. Similarly, [20] utilizes 32-bit data path and has power consumption in micro-watt level but the area requirements make it unsuitable for the small sensors.In [21], an asynchronous design has been presented for 128-bit data-path AES that consumes lesser power but the area requirements are high for the small devices and power consumption is still a concern for resource constrained devices. In [22], on FPGA, a simplified version of the AES algorithm is realised.…”

Section: Related Workmentioning

confidence: 99%

AES 32: An FPGA implementation of Lightweight-AES for IoT Devices

Singh Dhanda,

Singh,

Jindal

2024

IJCDS

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IoT is marked by the resource-constrained devices. Information security is the main challenge that arise due to wireless transmission of data by ubiquitous sensors. The rapid expansion of IoT setups with resource-constrained devices has spurred research into low-cost information security solutions. This study presents an efficient version of AES for high throughput. The AES's data path is 32-bit compressed. Implementation has been carried out on different FPGA families. Data path compression and use of BRAMs has led to improved throughput with savings in resource consumption. Loop-unrolled AES results in the consumption of 2669 slices which 12 times as big as this design. While 32-bit AES with 128-bit data path consumes 4 times more resources than proposed design which uses 223 slices and 5 BRAMs on Artix-7 FPGA. The proposed design delivers throughput in the range of 2.2 to 3.5 Gbps and achieves efficiency of 1.75 Mbps-7.8 Mbps per slice on different FPGAs. It outperforms different lightweight ciphers and constrained AES implementations in existing literature.

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Section: Related Workmentioning

confidence: 99%

AES 32: An FPGA implementation of Lightweight-AES for IoT Devices

Singh Dhanda,

Singh,

Jindal

2024

IJCDS

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“…Besides, compared with [7] that adopted the asynchronous dualrail circuit and delayed completion and performed only common SCA simulations with 5k power traces, we redesigned the asynchronous circuit units such as dualrail balanced circuits and dual-rail spacer latch and performed both common SCA and ML SCA with 200K power traces. Although these balanced gates and spacer latch increase area, our design outperforms in area compared with [7,28,29] because we reduce the number of S-boxes from 20 to 2. ( )*normalized data regarding the 65nm technology process…”

Section: Comparison With the State Of Art Designsmentioning

confidence: 99%

28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance

Zou

Cui

Dai

et al. 2021

IEICE Electron. Express

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An asynchronous Advanced Encryption Standard (AES) cryptographic processor for low-area and side-channel attack (SCA) resistant applications is introduced. To reduce the area and power, two Substituting Byte blocks (S-Boxes) are reused in key expansion and the data encryption module, respectively. To mitigate SCA, we adopt asynchronous dual-rail logic with dual-rail balanced logic and new dual-rail spacer latch. Common and Machine learning (ML) SCA simulations are performed to validate SCA resistance. To the best of our knowledge, we are the first ones to perform the ML SCA evaluations on asynchronous AES. Simulation results with 200K power traces demonstrate that our asynchronous AES is immune to the attacks. Our proposed asynchronous AES occupies an area of 0.016 2 in TSMC 28nm technology and consumes 1nJ per encryption at a supply voltage of 0.9V.

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“…All the strategies above are synchronous methods, but asynchronous design is usually known as a powerful low power strategy because asynchronous computational blocks can be designed to consume energy only when and where needed [12]. Asynchronous strategies have been applied to so many low power designs [13,14,15,16,17,18,19,20,21,22,23,24,25,26,27]. Several classic asynchronous low-power designs are briefly introduced in the following text.…”

Section: Introductionmentioning

confidence: 99%

“…Several classic asynchronous low-power designs are briefly introduced in the following text. In [14], a low power asynchronous AES core is presented and could cipher 128-bit data/key in 300 ns and consumes 5.47 mW. TrueNorth, a well-known neurosynaptic chip, is the largest chip developed at IBM Inc. with 5.4 billion transistors [18].…”

Section: Introductionmentioning

confidence: 99%

Design of low-power low-area asynchronous iterative multiplier

You

Hei

Jia

et al. 2019

IEICE Electron. Express

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In this paper, a 16 times 16 low-power low-area asynchronous iterative multiplier is proposed. The multiplier diminishes 2 bits at a time with an iterative structure, to filter out the useless switching activities, we employ a finishing detector to dynamically detect the end of the computation and stop iteration ahead of schedule. Additionally, with the employment of finishing detectors, the proposed multiplier could provide a much faster average speed than synchronous approach. Post-layout simulation results show that the asynchronous multiplier offers up to 74% power reduction compared with the synchronous design. Simultaneously, the proposed design also exhibits a prominent area reduction compared with other non-iterative multiplier benefited from the iterative architecture.

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130nm Low power asynchronous AES core

Cited by 9 publications

References 5 publications

AES 32: An FPGA implementation of Lightweight-AES for IoT Devices

AES 32: An FPGA implementation of Lightweight-AES for IoT Devices

28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance

Design of low-power low-area asynchronous iterative multiplier

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