28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance

Abstract

An asynchronous Advanced Encryption Standard (AES) cryptographic processor for low-area and side-channel attack (SCA) resistant applications is introduced. To reduce the area and power, two Substituting Byte blocks (S-Boxes) are reused in key expansion and the data encryption module, respectively. To mitigate SCA, we adopt asynchronous dual-rail logic with dual-rail balanced logic and new dual-rail spacer latch. Common and Machine learning (ML) SCA simulations are performed to validate SCA resistance. To the best of our knowledge, we are the first ones to perform the ML SCA evaluations on asynchronous AES. Simulation results with 200K power traces demonstrate that our asynchronous AES is immune to the attacks. Our proposed asynchronous AES occupies an area of 0.016 2 in TSMC 28nm technology and consumes 1nJ per encryption at a supply voltage of 0.9V.

A multi-level architecture for hardware Trojan and vulnerability runtime detection and response towards cryptographic IP

“…Analog sensors suffer from sensitivity to errors due to PVs and noise, which limits their application. Considering that cryptographic IP is a widely used type of IP to underpin the security foundation of sensitive content protection, memory encryption and network security [24,25,26], hardware Trojan and vulnerability detection and mitigation to third-party cryptographic IPs have not received sufficient attention. Reverse engineering techniques and combinatorial tests have been applied [27].…”