14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS

Sun, Xun; Boora, Akshat; Zhang, Wenbing; Pamula, Venkata Rajesh; Sathe, Visvesh

doi:10.1109/isscc.2019.8662298

Cited by 27 publications

(6 citation statements)

References 3 publications

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“…For high resolution, however, a long delay-chains are required, increasing the chip area and slowing down the speed of DLDO. Alternatively, leveltriggered event-driven ADCs have been increasingly adopted in DLDOs because of their shortest latency and clock-less operation [80]- [85]. Unlike time-domain ADCs, of which operation is strongly dependent on the clock, event-driven ADCs can immediately respond to new events.…”

Section: A Comparator and Analog-to-digital Converter (Adc)mentioning

confidence: 99%

“…For ADCs with higher resolution, the LCO can be further reduced because the ADC resolution is tightly related to the V REG accuracy at steady state. Therefore, multi-bit voltage quantizers or ADCs have been more attractively used in DLDOs recently [83]- [85].…”

Section: A Comparator and Analog-to-digital Converter (Adc)mentioning

confidence: 99%

“…To maintain fast transient responses across PVT variations, computational regulation techniques using autonomous and dynamic gain tracking schemes were recently proposed [85], [93]. In the computationally regulated DLDO in [85], the quantization error in V REG is detected by its autonomous gain tracker and suppressed by its solver block within the same cycle. As a result, the computationally regulated DLDO [85] can drive a cortex microprocessor with a fast transient response time of < 20 ns for a fast switching load current of 5.6 mA/0.1 ns.…”

Section: A Advanced Synchronous Dldosmentioning

confidence: 99%

“…In the computationally regulated DLDO in [85], the quantization error in V REG is detected by its autonomous gain tracker and suppressed by its solver block within the same cycle. As a result, the computationally regulated DLDO [85] can drive a cortex microprocessor with a fast transient response time of < 20 ns for a fast switching load current of 5.6 mA/0.1 ns. The DLDO using a dynamic-gain control scheme and all-digital auto-tuning engine [93] also achieves sub-cycle transient responses and demonstrates 55 ns of transient response time for a load current step of 40 mA/0.1 ns over process variations and aging.…”

Section: A Advanced Synchronous Dldosmentioning

confidence: 99%

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Architectural Advancement of Digital Low-Dropout Regulators

Akram

Hwang

2020

IEEE Access

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Digital Low-dropout (DLDO) regulators have been widely utilised for highly-efficient finegrained power delivery and management in system-on-chips (SoCs) due to their process scalability, ease of integration, and low-voltage operation. However, conventional DLDOs suffer gravely from the power-speed tradeoff, which arises from the use of sampling clocks. To obtain reasonable performance in the undershoot and recovery during load transient states, a large output capacitor is inevitably required in these DLDOs. Moreover, they inherently involve large steady-state voltage ripples and poor power-supply rejection (PSR). These limitations of synchronous DLDOs and their counter measures are thoroughly discussed in this paper. Various design strategies of major building blocks, i.e. comparators and power transistor arrays, are explained in detail with examples. Architectural advances are also expounded including state-of-the-art DLDO architectures such as clock-boosted synchronous, analog-assisted synchronous, asynchornous, eventdriven, and hybrid DLDOs. These state-of-the-art DLDOs do not only address the power-speed tradeoff and achieve fast load transient responses, but also can eliminate the use of an output capacitor in some cases. Moreover, some hybrid DLDOs successfully removed the steady state ripples and achieve high PSR. All of these DLDO are compared on basis of their performance metrics and figure-of-merits (FOMs).

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Section: A Comparator and Analog-to-digital Converter (Adc)mentioning

confidence: 99%

Section: A Comparator and Analog-to-digital Converter (Adc)mentioning

confidence: 99%

Section: A Advanced Synchronous Dldosmentioning

confidence: 99%

Section: A Advanced Synchronous Dldosmentioning

confidence: 99%

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Architectural Advancement of Digital Low-Dropout Regulators

Akram

Hwang

2020

IEEE Access

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“…However, the current highly synthesizable core logic design of DLDO cannot completely avoid using analog techniques or precise voltage references to help the voltage comparison process [3]- [13], which hinders further integration. In [7], an autonomous gain tracking technique is introduced to the digital LDO loop for fast and stable transient response across PVT. A flash analog-to-digital converter (ADC) is required for the voltage comparison, which is a complete analog design and not friendly for process scalability.…”

Section: Introductionmentioning

confidence: 99%

A Fully-Synthesizable Fast-Response Digital LDO Using Automatic Offset Control and Reuse

Liu

Zhao

Shi

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper proposes a fully synthesizable digital lowdropout (DLDO) regulator using an automatic offset control and reuse technique implemented in a 65-nm CMOS technology. To realize the fully synthesizable DLDO design, all components of core blocks are made with standard logic cells. The proposed offset control and reuse technique is adopted to cancel the offset voltage from the logic cells automatically, to provide the adaptive equivalent thresholds for the voltage comparison window, and to speed up the dropout voltage response. Besides, the modified comparator-triggered oscillator introduces the output of the comparator to the oscillation loop to choose the optimum clock edge in the delay line to feed back, which ensures both of the fast response and enough time margin for the comparator delay at the same time. The core area of the output-capacitance-less DLDO is 0.027 mm 2 . The simulated results show that a 100 mA step in load current produces a voltage drop of 140 mV with the response time of 1.2 ns. The steady-state error is less than 4 mV. The peak current efficiency is 99.9%.

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