14‐bit 20 μW column‐level two‐step ADC for 640 × 512 IRFPA

Abstract

A column-level two-step analogue-to-digital converter (ADC) structure for infrared focal-plane array (IRFPA) is proposed. The first step adopts a 16-column-shared 6-bit flash ADC to accomplish the coarse conversion of 16 columns one by one. Owing to the staggered code and correction, a dynamic comparator is adopted in the flash ADC and the power dissipation of a flash ADC averaged to one column in period is only 0.386 μW. The second step is SAR conversion of which the cycle time is prolonged. The input voltage variation of the comparator in the charge redistribution structure is decreased to tens of millivolts; so a 1.8 V power supply is adequate in spite of 5 V V FS. The power dissipation of this comparator is reduced to 5.966 μW. Also, the lower clock frequency of the SAR logic reduces the dynamic power. A 14-bit two-step ADC is designed in 0.18 μm process and the equivalent power dissipation of the proposed ADC structure for one column is <20 μW.

Current Input Pixel-Level ADC with High SNR and Wide Dynamic Range for a Microbolometer

“…Information can be transported with a high signalto-noise ratio (SNR) in a more power efficient manner in the digital domain using a monolithic ADC, and on-chip signal processing for system-on-chip (SoC) can be made available. Monolithic ADCs can be implemented at the chip level by employing a single high-speed ADC [7], at the column level by using multiple lower speed ADCs [8,9] or at the pixel level by using very low speed ADCs [10][11][12][13][14]. A pixel-level ADC has many advantages over chip and column level ADCs.…”