14 bit 50 MS/s 0.18 µm CMOS pipeline ADC based on digital error calibration

Lee, K.-H.; Kim, Y.-J.; Kim, K.-S.; Lee, S.-H.

doi:10.1049/el.2009.2013

Cited by 4 publications

(3 citation statements)

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“…In addition, a fast background calibration is proposed which needs less than 0.5 s to converge, much faster than Refs. [11,15,17]. All these techniques guarantee the high performance of the proposed ADC while consuming only 166 mW power at Nyquist rate.…”

Section: Introductionmentioning

confidence: 89%

“…[11], and 60 times than Refs. [15,17]. Besides, unlike correlation-based algorithms OE12 , this background calibration does not affect the dynamic range of MDAC.…”

Section: Background Calibrationmentioning

confidence: 99%

“…Several previous works propose some improvements to get good linearity performances for high-speed 14-bit pipeline ADC, e.g. Reference [15] uses a pseudorandom dithering for capacitor calibration and Reference [17] needs an on-chip memory to store the error codes for calibration also getting the required static linearity. However, in these works, the calibration needs more than one minute to attain the convergence which is not suitable for many shortlatency applications.…”

Section: Introductionmentioning

confidence: 99%

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A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB

Chen¹

2012

J. Semicond.

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This paper describes the design of a 14-bit 20 Msps analog-to-digital converter (ADC), implemented in 0.18 m CMOS technology, achieving 11.2 effective number of bits at Nyquist rate. An improved SHA-less structure and op-amp sharing technique is adopted to significantly reduce the power. The proposed ADC consumes only 166 mW under 1.8 V supply. A fast background calibration is utilized to ensure the overall ADC linearity.

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Section: Introductionmentioning

confidence: 89%

“…[11], and 60 times than Refs. [15,17]. Besides, unlike correlation-based algorithms OE12 , this background calibration does not affect the dynamic range of MDAC.…”

Section: Background Calibrationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB

Chen¹

2012

J. Semicond.

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A digital processor for full calibration of pipelined ADCs

Fardad

Frounchi

Karimian

2011

Analog Integr Circ Sig Process

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In this paper, a digital processor is presented for full calibration of pipeline ADCs. The main idea is to find an inverse model of ADC errors by using small number of the measured codes. This approach does not change internal parts of the ADC and most known errors are compensated simultaneously by digital post-processing of the output bits. Some function approximation algorithms are tested and their performances are evaluated. To verify the algorithms, a 12-bit pipelined ADC based on 1.5-bit per stage architecture is simulated with 1%-2% non-ideal factors in the SIMULINK with a 20 MHz sinusoidal input and a 100 MS/s sampling frequency. The selected algorithm has been implemented on a Virtex-4 LX25 FPGA from Xilinx. The designed processor improves the SNDR from 45 to 69 dB and increases the SFDR from 45.5 to 90 dB. The calibration processor also improves the integral nonlinearity of the ADC.

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