14nm FinFET technology SRAM cell margin evaluation and analysis by local layout effect

Mun, Seong Yeol; Burnett, D.; Lim, Kee Young; Parihar, Sanjay; Shi, Yong; Lo, Hsien-Ching; Wang, Hong; Lee, K. J.; Hu, Owen; Versaggi, Joseph; Jerome, C.; Lee, J. G.; Samavedam, Srikanth; Sohn, D. K.

doi:10.1109/s3s.2017.8309248

Cited by 2 publications

(1 citation statement)

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“…In this case, in order to grow the SiP EPI to the same height as before, the lateral growth will increase significantly leading to bridging of the EPI to an adjacent fin, which will cause a yield problem. This work discusses a method to achieve deeper cavities while keeping the same SiP EPI lateral growth by introducing the confined growth concept where the SiP EPI lateral width is controlled by the fin sidewall spacer to prevent the large SiP EPI short to the adjacent pFET EPI especially in the high-density SRAM (HD SRAM) area which typically has the minimum nFET and pFET spacing [10], as shown in figure 1. In this work, all splits have matched EPI width and no N-P short could be detected by a tailored defect scanning that focuses on the HD SRAM array.…”

Section: Introductionmentioning

confidence: 99%

Performance boost using spacer-confined cavity for advanced FinFET technology

Peng

Zhan

et al. 2018

Semicond. Sci. Technol.

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We present a method to form a spacer-confined cavity to enable the deeper cavity for performance improvement while keeping the lateral width of epitaxial silicon doped with phosphorous (SiP EPI) from creating an EPI bridging issue. An extra non-selective etch step is introduced to leave the sidewall spacer but etch away the Si fin. The SiP EPI is confined between the sidewall spacer for EPI lateral width control. In this work, TCAD simulation shows that the effective gate length (L eff ) near the bottom of the fin decreases when cavity depth increases. The deeper junction provides another performance boost on top of the performance improvement from the fin height increase. In addition, the spacer-confined cavity demonstrates a 6% device performance improvement with comparable drain-induced-barrier-lowering at +8 nm cavity depth. The device performance starts saturation when the cavity depth extends beyond +15 nm. The spacer-confined cavity offers a solution to increase cavity depth without suffering from the EPI bridging issue for advance finFET technology.

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Section: Introductionmentioning

confidence: 99%