In-situ Boron doped embedded SiGe epitaxy has been widely used for CMOS source/drain in advanced technology nodes, from its introduction in planar devices to its more recent application in FinFETs. Compared to planar technology, FinFETs have the benefit of an improved short channel effect, which enables significantly higher in-situ doping level for lower contact resistance. This work explores the source/drain expitaxy design differences between planar and FinFET transistors, and how the in-situ doped epitaxy process can be optimized to address the call for a higher doping level in the FinFET source/drain. Specifically, we observe a competing relationship between germanium and boron incorporation -- increasing Ge incorporation generally lowers boron doping, and increasing boron incorporation generally lowers Ge. Moreover, our work shows that the limit of boron doping can be boosted by increasing Ge percentage, and furthermore a Si-Ge-B phase diagram is proposed based on this experimental data. Defective epitaxy is observed outside of the soluble region of the phase diagram, featuring Boron-rich incoherent phase or Boron segregation. Finally, we present device data that show the performance benefit when Ge% and boron is optimized according to the phase diagram, characterized by lower Ron and higher drive current.

Epitaxy growth loading effect-the growth rate difference between device macros due to their local open ratio difference-is an important consideration for device design and thus process optimization. A poor loading process leads to device performance delta across macros. For eSiGe on FinFETs, we found that optimized eSiGe on FinFETs saturates as the eSiGe diamond pins at fin top surface and the fin-sidewall-spacer (FSS). The eSiGe diamond size measured by lateral CD does not increase with deposition time, but it linearly correlates to cavity depth and FSS pushdown. In principle, the eSiGe loading effect can be addressed with an extended growth time until every device macros saturates. However, it is found that, the epitaxy growth related defects, measured by abnormal eSiGe and unwanted growth, can also be elevated to an unacceptable level for a longer deposition time. Thus, the eSiGe loading process still needs to be optimized for an improved process window. In this work, an optimized eSiGe process achieves reduced loading between 2-fin and 40-fin macros and thus a smaller pFET performance gap between the two device macros.

Low-dielectric constant (low-k) material is critical for advanced FinFET technology parasitic capacitance reduction to enable lowpower and high-performance applications. Silicon Oxycarbonnitride (SiOCN) is one of the most promising low-k materials for FinFET gate sidewall spacer. The k value of SiOCN can be controlled in the range of 4.1-5.2 by modifying the chemical contents during the deposition process. However, the integration of SiOCN with k value lower than 5.2 for advanced FinFET technology faces substantial challenges associated with the material damage from subsequent manufacturing processes. Here, the authors demonstrate a hybrid low-k spacer scheme on a fully integrated 7 nm FinFET technology platform, in which SiOCN with k value of 4.5 was successfully integrated along the sidewalls of the gate electrode as spacer while retaining the structural integrity and dielectric properties. Device characterisation on the hybrid low-k spacer scheme (k = 4.5) demonstrated 12/11% reduction in P/NFET overlap capacitance (C OV) and 3% reduction in ring oscillator effective capacitance (C EFF) in comparison to the baseline reference using SiOCN with k value of 5.2 as spacer. Furthermore, reliability characterisation confirmed the dielectric breakdown voltage (V BD) and leakage current (I LKG) of the hybrid low-k spacer (k = 4.5) were comparable to the baseline reference (k = 5.2), meeting the technology requirements.

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This work reports that, for the first time, the engineering of eSiGe proximity and eSiGe layer-one (L1) thickness modulates gate oxide integrity and device performance simultaneously in the leading edge FinFET technology. It is observed that there is a tradeoff between the benefit of transistor performance and the cost of gate oxide breakdown voltage (Vbd) degradation. TEM analysis indicates that eSiGe L1 is exposed to interfacial-layer/high-K in replaced-metal-gate (RMG) processes, suggesting gate oxide Vbd is compromised by germanium oxide formation at the L1 and high-k boundary. Thus, the strategy of FinFET junction optimization needs to consider not only transistor performance but also the gate oxide integrity.