Using a combination of dimensional analysis and large deformation finite element simulations of triple indentations of 120 materials, a framework for capturing the indentation response of transversely isotropic materials is developed. By considering 4800 combinations of material properties within the bounds of the original set of 120 materials, forward algorithms that predict the indentation response of materials and reverse algorithms that predict the materials' elastic and plastic properties from experimentally measured indentation responses are formulated for both longitudinal and transverse indentations. Issues of accuracy, reversibility, uniqueness and sensitivity within the context of the indentation of transversely isotropic materials are addressed carefully. Using 1400 combinations of material properties, it is demonstrated that there is perfect reversibility between the material properties and their indentation responses as predicted by the forward and reverse algorithms. On average, the differences between the results of the finite element analysis and those predicted by the forward algorithms for longitudinal or transverse indentations are less than 1%, thus demonstrating the high accuracy and uniqueness of the forward analysis. For longitudinal and transverse indentations, the reverse algorithms provide accurate results in most cases with an average error of 3 and 6%, respectively. A sensitivity analysis with a ±2% variation in the material properties in the forward algorithm and ±2% variation in the indentation responses in the reverse algorithms demonstrated the robustness of the algorithms developed in the present study, with the longitudinal indentations providing relatively less sensitivity to variability in indentation responses as compared to the transverse indentations.

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This work reports that, for the first time, the engineering of eSiGe proximity and eSiGe layer-one (L1) thickness modulates gate oxide integrity and device performance simultaneously in the leading edge FinFET technology. It is observed that there is a tradeoff between the benefit of transistor performance and the cost of gate oxide breakdown voltage (Vbd) degradation. TEM analysis indicates that eSiGe L1 is exposed to interfacial-layer/high-K in replaced-metal-gate (RMG) processes, suggesting gate oxide Vbd is compromised by germanium oxide formation at the L1 and high-k boundary. Thus, the strategy of FinFET junction optimization needs to consider not only transistor performance but also the gate oxide integrity.

In 2X nm devices, high-k metal gate have become an essential part of emerging devices. Wet cleaning plays an important part of advanced semiconductor manufacturing process. As the technology node advances, it has become more and more challenging. Presence of organic residues and cluster of particles on product wafers can cause lot of issues. These clusters of particles and organic residues are found to be die killers and hence, reduce the yield of the product. In this work, we will focus on root cause finding for the organic residue and clusters. The proposed solution demonstrates the improvement of 11X and yield gain of 3.5% as compare to product wafers, and cost savings for HVM (high volume manufacturing).

In the advanced nodes of 28nm and below, small defects too can have a significant impact on the final yield results of wafers. As the technology node advances it has become increasingly challenging to control the extent of defects while also ensuring that the desired processing parameters are in place. In this paper we evaluate the influence of various processing parameters on the extent of "Unwanted Growth" defects on wafers in the form of small SiGe nodules (20-50nm) left over post selective SiGe epitaxial growth for strained CMOS Si. These defects, depending on where they grow/land, can lead to failure of the chip. An optimization of the processing parameters to minimize the occurrence of these defects leads to yield gain and cost savings for High Volume Manufacturing (HVM).