15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing

Jia, Huang; Ozatay, Murat; Tang, Yongxin; Valavi, Hossein; Pathak, Rakshit; Lee, Jinseok; Verma, Naveen

doi:10.1109/isscc42613.2021.9365788

Cited by 113 publications

(66 citation statements)

References 5 publications

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“…At an operation frequency of 1 GHz and a supply voltage of 0.8 V, the HERMES core shows a peak throughput of 1.008 TOPS at an efficiency of 10.5 TOPS/W, when running the MNIST-based experiment as described above. Compared to the (shown in Table I), the measured throughput density of 1.59 TOPS/mm 2 is significantly higher than recent non-volatile ReRAM-based designs [24], [45] and also slightly higher than recent SRAM + capacitor-based designs [44], when 8-bit input quantization is used. Only the SRAM-based design in [46] shows a better throughput density, given by its compact 8T SRAM unit-cell design employing push-rules and the advanced manufacturing node.…”

Section: System-level Performancementioning

confidence: 69%

“…By selecting the appropriate D flip-flop that receives A, the increment size of the counter can be made variable. This allows the execution of shift-and-add operations within the ADC at a minimal overhead, avoiding dedicated multi-bit adders [42]- [44]. Hence, we enabled bit-serial input modulation in addition to the conventional multi-bit pulsewidth modulation (PWM).…”

Section: Counter With Variable Increment Sizementioning

confidence: 99%

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HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh

Stanisavljević

Mas

et al. 2022

IEEE J. Solid-State Circuits

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We present a 256 × 256 in-memory compute (IMC) core designed and fabricated in 14-nm CMOS technology with backend-integrated multi-level phase change memory (PCM). It comprises 256 linearized current-controlled oscillator (CCO)-based A/D converters (ADCs) at a compact 4-µm pitch and a local digital processing unit (LDPU) performing affine scaling and ReLU operations. A frequency-linearization technique for CCO is introduced, which increases the maximum Manuscript

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Section: System-level Performancementioning

confidence: 69%

Section: Counter With Variable Increment Sizementioning

confidence: 99%

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh

Stanisavljević

Mas

et al. 2022

IEEE J. Solid-State Circuits

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“…The accumulated current (in the case of pulse amplitude-based encoding) or the accumulated charge (in the case of pulse-width encoding) across each bitline is indicative of the dot product between the input vector and one column of the matrix. Owing to the reduction in matrix data transfers, parallelism and analog mode of operation, in-memory computing allows to perform MVMs at high energy efficiency (>10 TOPS/W) [3,4]. Thus, in-memory computing can be a viable alternative to conventional GPU-based and other digital solutions for MVM acceleration, which is critical for many applications including deep learning.…”

Section: Introductionmentioning

confidence: 99%

Precision of bit slicing with in-memory computing based on analog phase-change memory crossbars

Gallo

Nandakumar

Ciric

et al. 2022

Neuromorph. Comput. Eng.

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In-memory computing is a promising non-von Neumann approach to perform certain computational tasks efﬁciently within memory devices by exploiting their physical attributes. However, the computational accuracy achieved with this approach has been rather low, owing to signiﬁcant inter-device variability and inhomogeneity across an array as well as intra-device variability and randomness from the analog memory devices. Bit slicing, a technique for constructing a high precision processor from several modules of lower precision, is a promising approach for overcoming this accuracy limitation. However, a systematic study to assess the precision ultimately achieved by bit slicing with analog in-memory computing has so far been lacking. In this work, we assess the computational error from bit slicing when performing in-memory matrix-vector multiplications. Using accurate models of phase-change memory crossbar arrays, we demonstrate that unlike in digital processors where bit slicing is used to extend the dynamic range of the number representation, bit slicing with in-memory computing should aim at minimizing the error from the analog matrix representation through averaging within a given dynamic range. The results are validated using a prototype phase-change memory chip and the impact on the neural network inference accuracy on CIFAR-10 and ImageNet benchmarks is evaluated.

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“…I N-MEMORY computing (IMC) circuits reduce data transfer by performing computations inside the memory without transferring data to processing units [1]- [6]. IMC circuits for accelerating deep neural networks (DNNs) typically implement crucial operations such as Multiply-Accumulate/Average (MAC/MAV) and activation functions (e.g., Rectified Linear Unit, ReLU).…”

Section: Introductionmentioning

confidence: 99%

An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network

Kim

Lee

Kim

et al. 2022

IEEE Trans. Circuits Syst. II

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In-Memory Computing (IMC) has been widely studied to mitigate data transfer bottlenecks in von Neumann architectures. Recently proposed IMC circuit topologies dramatically reduce data transfer requirements by performing various operations such as Multiply-Accumulate (MAC) inside the memory. In this paper, we present an SRAM macro designed for accelerating Memory-Augmented Neural Network (MANN). We first propose algorithmic optimizations for a few-shot learning algorithm employing MANN for efficient hardware implementation. Then, we present an SRAM macro that efficiently accelerates the algorithm by realizing key operations such as L1 distance calculation and Winner-Take-All (WTA) operation through mixed-signal computation circuits. Fabricated in 40nm LP CMOS technology, the design demonstrates 27.7 TOPS/W maximum energy efficiency, while achieving 93.40% and 98.28% classification accuracy for 5-way 1-shot and 5-way 5-shot learning on the Omniglot dataset, which closely matches the accuracy of the baseline algorithm.

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15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing

Cited by 113 publications

References 5 publications

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Precision of bit slicing with in-memory computing based on analog phase-change memory crossbars

An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network

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15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing

Cited by 113 publications

References 5 publications

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Precision of bit slicing with in-memory computing based on analog phase-change memory crossbars

An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network

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Product

Resources

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HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs