150 mm SiC Engineered Substrates for High-Voltage Power Devices

Abstract

Silicon Carbide (SiC) Power Devices have emerged as a breakthrough technology for a wide range of applications in the frame of high power electronics. Despite the continuously improving quality and supply of 4H-SiC substrates, the availability of such wafers is still insufficient. An advantageous opportunity is offered by the Smart CutTM technology with the integration of a very high quality SiC layer transferred to a low resistivity handle wafer. This bi-layer material enables a significant yield optimization and improvement of the device’s electrical performance. Moreover, an additional key feature of the Smart CutTM technology is the possibility to re-use multiple times the donor wafer, leading to reduced manufacturing costs and enabling the high volume production of SiC wafers. In this paper we report the latest advances in the development of such so called SmartSiCTM substrates.

Benchmarking Experiment of Substrate Quality including SmartSiC^TM Wafers by Epitaxy in a Batch Reactor

“…All wafers were characterized using UVPL imaging plus DIC/optical microscopy and all full stack epilayers with XRT for defectivity after the epitaxial process or thermal etching. buffer only target 1 µm (1) 1.20E18 cm -3 no drift layer heat up & cool down no growth in this experiment (1) 1µm is below the reliable range of the FTIR thickness measurement system used These X-ray topography measurements were carried out according to the Lang method using the (0008) reflex of Cu Kα radiation using an anode power of 1.2kW (40kV, 30mA) and a scanning speed of 30mm/min on the full wafer area. A CCD detector with a pixel pitch of 5.4µm and a distance to the sample surface of 60mm was used in time-delay integration (TDI) mode to capture the topograms.…”

“…In addition, the device performance can be strongly enhanced thanks to lower device conduction and/or switching losses using ultra high conductivity receiver substrates. SOITEC's Smart Cut™ process [1] yields such a 0.6 µm thin SiC layer, which is transferred to a polycrystalline SiC carrier substrate and bonded thanks to a conductive bonding, called SmartSiC™ substrate.…”

Evaluation of Crystal Quality and Dopant Activation of Smart Cut^TM - Transferred 4H-SiC Thin Film

“…In order to characterize both the crystal quality and its dopant reactivation, three series of samples were prepared as follows. 1-Commercial wafers of 4°-off axis, 4.10 18 cm -3 N-doped bulk 4H-SiC were H + -implanted as conventional SmartSiC™ substrates [3], before annealing up to 800°C for 30 minutes. This first series served for both crystallinity recovery (Raman, RBS) and dopant activation analysis.…”

“…In this extent, the Smart Cut™ process offers a state-of-the art opportunity to overcome this challenge. Significant yield optimization and performance improvements have been achieved by combining the benefits of an ultra-low resistivity polycrystalline handle and of a high quality 4H-SiC transferred layer [3]. The crystalline quality and the electrical activation of the 4H-SiC transferred layer are then at stake when it comes to the power device reliability.…”

Proven Power Cycling Reliability of Ohmic Annealing Free SiC Power Device through the Use of SmartSiC^TM Substrate

“…Despite continuous improvement in 4H-SiC material quality and supply, the availability of high quality wafers, enabling very high yields, is still inadequate. The Smart Cut™ technology enables the integration of high quality SiC layer transfer for device yield optimization, combined with a low resistivity handle wafer (<5mOhm.cm) to improve device conduction and switching losses [1,3]. The SmartSiC™ engineered substrate is composed of a thin (between 350 and 800nm) high-quality 4H-SiC layer bonded (conductive bonding) on top of a 350µm thick polycrystalline SiC handle wafer.…”