Silicon Carbide (SiC) Power Devices have emerged as a breakthrough technology for a wide range of applications in the frame of high power electronics. Despite the continuously improving quality and supply of 4H-SiC substrates, the availability of such wafers is still insufficient. An advantageous opportunity is offered by the Smart CutTM technology with the integration of a very high quality SiC layer transferred to a low resistivity handle wafer. This bi-layer material enables a significant yield optimization and improvement of the device’s electrical performance. Moreover, an additional key feature of the Smart CutTM technology is the possibility to re-use multiple times the donor wafer, leading to reduced manufacturing costs and enabling the high volume production of SiC wafers. In this paper we report the latest advances in the development of such so called SmartSiCTM substrates.

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The Smart CutTM process offers an advantageous opportunity to provide a large number of performance-improved SiC substrates for power electronics. The crystalline quality and the electrical activation of the 4H-SiC transferred layer are then at stake when it comes to the power device reliability. In this study, we find that the H+ ion implantation used for the Smart CutTM process leads to electrical deactivation of dopants and partially disorders the material. The transferred layer fully recovers its initial crystalline quality after a 1300°C anneal, with no further evolution beyond this temperature. At this point however, the n-type dopants are still inactive. The dopant reactivation occurs in the same temperature range than that of implanted nitrogen: between 1400°C and 1700°C. After 1700°C, the initial doping level of bulk SiC is recovered.

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The Smart CutTM technology enables the combination of a high quality single crystal SiC layer onto a low resistivity handle wafer (<5mOhm.cm), allowing device optimization as well as the reduction of device’s conduction and switching losses. On this new SmartSiCTM substrate, the sheet resistance of the back side contact after metal deposition, without anneal, is about 10x lower than the annealed back side contact on 4H-SiC. Schottky-barrier vertical structures thinned down to 250μm were prepared for power cycling tests (PCT) measurements. Up to 250 k cycles, the devices remained within the specifications of AQG324 for samples prepared from SmartSiCTM substrates. We are demonstrating here that in addition to a higher current rating (up to 20%), the SmartSiCTM substrate enables a device fabrication simplification by skipping the annealing of the back-side ohmic contact, without compromising either the back-side contact resistance or the assembly PCsec reliability.