150mV sub-threshold Asynchronous multiplier for low-power sensor applications

Crop, Joseph; Fairbanks, S.; Pawłowski, Robert; Chiang, Patrick

doi:10.1109/vdat.2010.5496737

Cited by 9 publications

(8 citation statements)

References 9 publications

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“…(1) Proposed area model: Total silicon area consumed A T DMR by a The area evaluated is with respect to module library generated with complementary metal-oxide-semiconductor 90 nm technology node [30][31][32]. The area model therefore accurately captures the most important portions of a datapath including steering logic such as multiplexers and demultiplexers, storage hardware such as buffers, error detection block such as comparator and FUs hardware described in the form of transistors.…”

Section: Evaluation Modelsmentioning

confidence: 99%

Low‐cost security aware HLS methodology

Sengupta

Bhadauria

Mohanty

2017

IET Computers & Digital Techniques

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Owing to massive complexity of modern digital integrated circuits (ICs) disabling complete in-house development, globalisation of the design process establishes itself as an inevitable solution for faster and efficient design. However, globalisation incurs importing intellectual property (IP) cores from various third party vendors, rendering an IP susceptible to hardware threats. To provide trust and security in digital ICs within user constraints, design of a low-cost optimised dual modular redundant, through Trojan secured high-level synthesis (HLS) methodology, is crucial. This study presents exploration of a lowcost optimised HLS solution capable of handling hardware Trojan (providing security) that alters computational output. The key contributions of the study are as: (i) novel low-cost security-aware HLS approach; (ii) novel encoding for representing bacterium in the design space (comprising of candidate datapath resource configuration and vendor allocation information for Trojan secured solution); and (iii) novel exploration process of an efficient vendor allocation procedure that assists in yielding a low-cost Trojan secured schedule. Experimental results indicate significant reduction in the cost of security-aware HLS solution (82.4%) through the proposed approach compared with a recent approach.

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Section: Evaluation Modelsmentioning

confidence: 99%

Low‐cost security aware HLS methodology

Sengupta

Bhadauria

Mohanty

2017

IET Computers & Digital Techniques

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“…Area comprises of components due to hardware resources, interconnect units, and storage units due to overhead incurred from buffering during storage of operation output.The area is evaluated with respect to module library according to CMOS 90nm technology node (adopted from [30] and [31]). …”

Section: B Proposed Area Modelmentioning

confidence: 99%

Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis

Sengupta

Bhadauria

2016

IEEE Access

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The challenges in the current design process for consumer electronics products include greater complexity and stiff time-to-market pressure, which has led to the usage of reusable intellectual property (IP) cores (such as JPEG and MPEG) as a sustainable solution. This has led to the domain of IP protection for anti-piracy as an important subject of research for a system design. Watermarking is expected to provide the best protection of authorship when applied at higher levels, i.e., during high-level synthesis. It is also well acknowledged that watermark insertion is non-trivial, as it is very difficult to choose a strong signature that results in higher security and less area overhead among available design solutions. This paper presents a novel multi-variable signature encoding for embedding a dynamic watermark in an IP design during architectural synthesis that provides enhanced security against typical attacks. Owing to the involvement of multiple (four) variables in the proposed signature, it is difficult to realize the signature without complete encoding knowledge of the four variables. Second, our approach aims to optimize the embedding cost of the watermark by exploring a low-cost solution through particle swarm optimization-driven design space exploration based on area-delay constraints. Comparison with a recent technique indicated that our watermark incurs lower embedding cost, lower runtime, and less storage hardware.INDEX TERMS IP security, watermark, design abstraction, high level synthesis, design space exploration, particle swarm optimization, optimization, area-delay constraints.

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“…Many synchronous multipliers exist [1], and some non-robust [2][3][4][5][6][7][8][9][10][11][12], and few robust asynchronous multiplier designs [13][14][15][16] have been reported in the literature. References [2][3][4][5][6][7][8][9][10][11][12] discuss different asynchronous multiplier designs, which are either full-custom or semi-custom designs and make use of a non-robust, non-delay insensitive two-phase bundled-data asynchronous handshake protocol for data processing and communication. Although bundled-data asynchronous multipliers are likely to be better off than the synchronous multipliers due to the formers' ability to achieve average-case speed performance and low power compared to the worst-case speed performance of the latter, they are not robust.…”

Section: Introductionmentioning

confidence: 99%

Speed, energy and area optimized early output quasi-delay-insensitive array multipliers

2020

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Multiplication is a widely used arithmetic operation that is frequently encountered in microprocessing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive double-rail data encoding and four-phase return-to-zero (RTZ) handshaking and four-phase return-to-one (RTO) handshaking. In this context, this article makes two contributions: (i) the design of a new asynchronous partial product generator, and (ii) the design of a new asynchronous half adder. We analyze the usefulness of the proposed partial product generator and the proposed half adder to efficiently realize QDI array multipliers. When the new partial product generator and half adder are used along with our indicating full adder, significant reductions are achieved in the design metrics compared to the optimum QDI array multiplier reported in the literature. The cycle time is reduced by 17%, the area is reduced by 16.1%, the power is reduced by 15.3%, and the product of power and cycle time is reduced by 29.6% with respect to RTZ handshaking. On the other hand, the cycle time is reduced by 13%, the area is reduced by 16.1%, the power is reduced by 15.2%, and the product of power and cycle time is reduced by 26.1% with respect to RTO handshaking. Further, the RTO handshaking is found to be preferable to RTZ handshaking to achieve slightly improved optimizations in the design metrics. The QDI array multipliers were realized using a 32/28nm complementary metal oxide semiconductor (CMOS) process technology.

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150mV sub-threshold Asynchronous multiplier for low-power sensor applications

Cited by 9 publications

References 9 publications

Low‐cost security aware HLS methodology

Low‐cost security aware HLS methodology

Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis

Speed, energy and area optimized early output quasi-delay-insensitive array multipliers

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