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A two-channel micro-power incremental ADC, designed for biosensor interface circuits, is reported. It uses a noise-coupled multi-bit delta-sigma loop, integrated with a novel digital decimation filter operating in near-threshold. It was realized in the IBM 90 nm CMOS technology. The fabricated 90nm CMOS prototype device, for a 1 V pp differential input range, experimentally shows a 74dB SNDR up to 2 kHz (1 kHz/channel) signal bandwidth. The total measured power consumption of the modulator is 13.5 µW.

A 4-bit Asynchronous multiplier was designed in the sub-threshold regime. The multiplier, using asynchronous completion detection, is more tolerant to process variation than conventional synchronous sub-threshold circuits and operates with a supply voltage as low as 150mV. The average energy per computation was simulated at 1.13pJ. The minimum energy voltage was simulated at 350mV, with an average micro-pipelined frequency of 11.3 kHz.

This work details a process-portable test chip, fabricated in 65nm CMOS, specifically designed to measure radiation-induced soft error rate (SER) during operation at near-threshold. A variety of SRAM, register file (RF), and digital logic test structures are included that provide a comprehensive assessment of circuit sensitivities to radiation at low V DD . Neutron irradiation measurements of SRAM/RF show a 6.45x increase in SER when V DD is lowered from 1.0V to 0.33V, and a 2.6x increase in multi-bit upsets. Alpha bombardment of digital logic tests demonstrates the effectiveness of this test chip platform in characterizing the relationship between SER and different circuit characteristics when operating at low V DD .

While Moore's law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit J. Low Power Electron. Appl. 2011, 1 335 approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well.