Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS

Pawłowski, Robert; Crop, Joseph; Cho, Minki; Tschanz, James; De, Vivek; Fairbanks, Thomas D.; Quinn, Heather; Borkar, S.; Chiang, Patrick

doi:10.1109/cicc.2014.6946138

Cited by 13 publications

(7 citation statements)

References 9 publications

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“…By checking the sensitivity trends in Figure 2, it can also be observed that the SBU sensitivity significantly increases at very low voltages, especially at near-threshold ones, contrarily to that of MCUs. This trend is consistent with the results presented by Pawlowski et al [21], where it can observed that the sensitivity for all types of MCUs barely increased in the range of 0.3V-1.0V.…”

Section: B Discussionsupporting

confidence: 82%

Sensitivity Characterization of a COTS 90-nm SRAM at Ultra Low Bias Voltage

Clemente

Hubert

Franco

et al. 2017

IEEE Trans. Nucl. Sci.

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Abstract-This paper presents the characterization of the sensitivity to 14-MeV neutrons of a Commercial Off-The-Shelf (COTS) 90-nm Static Random Access Memories (SRAMs) manufactured by Cypress Semiconductor, when biased at ultra low voltage. Firstly, experiments exposing this memory at 14-MeV neutrons, when powering it up at bias voltages ranging from 0.5V to 3.3V, are presented and discussed. These results are in good concordance with theoretical predictions issued by the modeling tool MUSCA-SEP 3 (MUlti-SCAles Single Event Phenomena Predictive Platform). Then, this tool has been used to obtain Soft Error Rate (SER) predictions at different altitudes above the Earth's surface of this device vs. its bias voltage. Finally, the effect of contamination by α particles has also been estimated at said range of bias voltages.

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Section: B Discussionsupporting

confidence: 82%

Sensitivity Characterization of a COTS 90-nm SRAM at Ultra Low Bias Voltage

Clemente

Hubert

Franco

et al. 2017

IEEE Trans. Nucl. Sci.

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“…The charts display all the rounds of reading that were made (in some cases, several rounds were carried out at the same VCC). The experimental data observed for the 90-nm SRAM is consistent with the results presented by Pawlowski et al [18], where it can be observed that the sensitivity for all types of MCUs barely increased in the range of 0.3V-1.0V. It is also consistent with the results obtained in 2015 in another sample of the same memory, presented in our previous work [10].…”

Section: A Sbu/mcu Sensitivitysupporting

confidence: 82%

SEU Characterization of Three Successive Generations of COTS SRAMs at Ultralow Bias Voltage to 14.2-MeV Neutrons

Clemente

Hubert

Fraire

et al. 2018

IEEE Trans. Nucl. Sci.

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Abstract-This paper presents a SEU sensitivity characterization at ultra-low bias voltage of three generations of COTS SRAMs manufactured in 130 nm, 90 nm and 65 nm CMOS processes. For this purpose, radiation tests with 14.2 MeV neutrons were performed for SRAM power supplies ranging from 0.5 V to 3.15 V. The experimental results yielded clear evidences of the SEU sensitivity increase at very low bias voltages. These results have been cross-checked with predictions issued from the modeling tool MUlti-SCAles Single Event Phenomena Predictive Platform (MUSCA-SEP 3 ). Large-scale SELs and SEFIs, observed in the 90-nm and 130-nm SRAMs respectively, are also presented and discussed.

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“…Combinational logic circuits are significantly less susceptible to soft errors and do not pose a concern [18], [14]. We address both single-event upsets (SEUs) and single-event multiple upsets (SEMUs) [19], [17]. While CLEAR can address soft errors in various digital components of a complex System-on-a-Chip (including uncore components [20] and hardware accelerators), a detailed analysis of soft errors in all these components is beyond the scope of this paper.…”

Section: Introduction His Paper Addresses the Cross-layer Resilienmentioning

confidence: 99%

“…Although the soft error rate of an SRAM cell or a flip-flop stays roughly constant or even decreases over technology generations, the system-level soft error rate increases with increased integration [12], [13], [14], [15]. Moreover, soft error rates can increase when lower supply voltages are used to improve energy efficiency [16], [17]. We focus on flip-flop soft errors because design techniques to protect them are generally expensive.…”

mentioning

confidence: 99%

“…Combinational logic circuits are significantly less susceptible to soft errors and do not pose a concern [18], [14]. We address both single-event upsets 1 Other error sources (voltage noise and circuit-aging) may be incorporated into CLEAR, but are not the focus of this paper.Eric Cheng, Student Member, IEEE, Shahrzad Mirkhani, Member, IEEE, Lukasz G. Szafaryn, Chen-Yong Cher, Senior Member, IEEE, Hyungmin Cho, Kevin Skadron, Fellow, IEEE, Mircea R. Stan, Fellow, IEEE, Klas Lilja, Member, IEEE, Jacob A. Abraham, Fellow, IEEE, Pradip Bose, Fellow, IEEE, and Subhasish Mitra, Fellow, IEEE Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience) T 2 (SEUs) and single-event multiple upsets (SEMUs) [19], [17]. While CLEAR can address soft errors in various digital components of a complex System-on-a-Chip (including uncore components [20] and hardware accelerators), a detailed analysis of soft errors in all these components is beyond the scope of this paper.…”

mentioning

confidence: 99%

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Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)

Cheng

Mirkhani

Szafaryn

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We present CLEAR (Cross-Layer Exploration for Architecting Resilience), a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to reliability failures: achieve desired resilience targets at minimal costs (energy, power, execution time, area) by combining resilience techniques across various layers of the system stack (circuit, logic, architecture, software, algorithm). This is also referred to as cross-layer resilience. In this paper, we focus on radiation-induced soft errors in processor cores. We address both single-event upsets (SEUs) and single-event multiple upsets (SEMUs) in terrestrial environments. Our framework automatically and systematically explores the large space of comprehensive resilience techniques and their combinations across various layers of the system stack (586 cross-layer combinations in this paper), derives cost-effective solutions that achieve resilience targets at minimal costs, and provides guidelines for the design of new resilience techniques. We demonstrate the practicality and effectiveness of our framework using two diverse designs: a simple, in-order processor core and a complex, out-of-order processor core. Our results demonstrate that a carefully optimized combination of circuit-level hardening, logic-level parity checking, and micro-architectural recovery provides a highly cost-effective soft error resilience solution for general-purpose processor cores. For example, a 50× improvement in silent data corruption rate is achieved at only 2.1% energy cost for an out-of-order core (6.1% for an in-order core) with no speed impact. However, (application-aware) selective circuit-level hardening alone, guided by a thorough analysis of the effects of soft errors on application benchmarks, provides a cost-effective soft error resilience solution as well (with ~1% additional energy cost for a 50× improvement in silent data corruption rate).Index Terms-Cross-layer resilience; soft errors I. INTRODUCTION HIS paper addresses the cross-layer resilience challenge for designing robust digital systems: given a set of resilience techniques at various abstraction layers (circuit, logic, architecture, software, algorithm), how does one protect a given design from radiation-induced soft errors using (perhaps) a combination of these techniques, across multiple abstraction layers, such that overall soft error resilience targets are met at minimal costs (energy, power, execution time, area)? Specific soft error resilience targets addressed in this paper are: Silent Data Corruption (SDC), where an error causes the system to output an incorrect result without error indication; and, Detected but Uncorrected Error (DUE), This research is supported in part by DARPA, DTRA, NSF, and SRC. The views expressed are those of the authors and do not reflect the official policy or position of the Department of Defense or the U.S. Government.E. Cheng, S. Mirkhani, and S. Mitra are with Stanford University (e-mail: eccheng@ stanford.edu).H. Cho is w...

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Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS

Cited by 13 publications

References 9 publications

Sensitivity Characterization of a COTS 90-nm SRAM at Ultra Low Bias Voltage

Sensitivity Characterization of a COTS 90-nm SRAM at Ultra Low Bias Voltage

SEU Characterization of Three Successive Generations of COTS SRAMs at Ultralow Bias Voltage to 14.2-MeV Neutrons

Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)

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