A 12-bit 7 &amp;#x00B5;W/channel 1 kHz/channel incremental ADC for biosensor interface circuits

Chen, Chia-Hung; Crop, Joseph; Chae, Jeongseok; Chiang, Patrick; Temes, Gábor C.

doi:10.1109/iscas.2012.6271940

Cited by 20 publications

(10 citation statements)

References 6 publications

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“…The input signal must be held constant during both conversion steps. Recent sensor applications require a signal bandwidth up to several kHz, for example, in bio-potential acquisition systems [4], [5], [8], [9], [33]. Thus, even though the zoom ADC can measure a DC signal with ex- traordinary energy efficiency, an energy-efficient high-accuracy ADC is still required to convert wide-band signals.…”

Section: The Proposed Two-step Incremental Adcmentioning

confidence: 99%

“…In addition, often the integrated ADC must be multiplexed among many channels. In applications requiring hundreds of channels, such as image sensor [10], [11] or bio-potential acquisition [4], [5], [8], [9], the integrated ADCs must be highly efficient in terms of power and chip area SoC.…”

Section: Introductionmentioning

confidence: 99%

“…Incremental analog-to-digital converters (IADCs) are often the best choice in low-frequency high-resolution sensor interfaces [1], [3], [6]- [8] . Their advantages [6], [7], [12] include simpler decimation filtering, easy multiplexing, and low latency.…”

Section: Introductionmentioning

confidence: 99%

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A Micro-Power Two-Step Incremental Analog-to-Digital Converter

Chen

Zhang

et al. 2015

IEEE J. Solid-State Circuits

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Integrated sensor interface circuits require energy-efficient high-resolution data converters. This paper proposes a twostep incremental A/D converter (IADC) which extends the performance of an th-order IADC close to that of a th-order IADC. The implemented device uses the circuitry of a second-order IADC (IADC2) to achieve close to third-order SNR performance. The proposed circuit does not require very high opamp DC gain; the gain can be as low as 60 dB for 100 dB SNR data conversion. The implemented IADC achieves a measured dynamic range of 99.8 dB, and an SNDR of 91 dB for a maximum input 2.2 V and a bandwidth of 250 Hz. Fabricated in 65 nm CMOS, the IADC's core area is 0.2 mm 2 , and it consumes only 10.7 µW. The measured FoMs are 0.76 pJ/conversion and 173.5 dB, both among the best reported results for IADCs. The measured results verify that the proposed two-step IADC is a more energy-efficient data conversion scheme than conventional high-order IADCs.Index Terms-Analog-to-digital converter (ADC), chopper stabilization, decimation filter, delta sigma ( ), extended-counting, flicker noise elimination, incremental data converters, low power, measurement and instrumentation, multi-stage noise shaping (MASH), multi-step, sensor interface, time-domain signal processing, two step.

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Section: The Proposed Two-step Incremental Adcmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Micro-Power Two-Step Incremental Analog-to-Digital Converter

Chen

Zhang

et al. 2015

IEEE J. Solid-State Circuits

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“…The feature of one-to-one mapping between input and output, providing precise high-resolution conversion with low offset and gain errors makes them suitable for the requirement of instrument and measurement (I&M) applications [8][9][10]. A 16 bit third-order cascaded-integrator feed-forward (CIFF) IΣΔ ADC is employed to digitized analog signal in this AFE IC.…”

Section: Implementation Of Incremental σδ Adcmentioning

confidence: 99%

A high dynamic range analog-front-end IC for electrochemical amperometric and voltammetric sensors

Liu

Chen

et al. 2015

Microelectronics Journal

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“…However, it has a complex architecture and needs too many clock cycles for a high-resolution ADC. The multi-bit incremental ADC alleviates the speed problem of the single-bit incremental ADC [14], [15]. As the resolution of the quantizer is increased by 1-bit, the number of samplings, which is represented as an incremental steps , is reduced by half, so the operating speed is increased.…”

mentioning

confidence: 99%

A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits

Hong

Kwon

2015

IEEE Trans. Circuits Syst. I

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This paper proposes a multi-bit incremental analog-to-digital converter (ADC) based on successive approximation (SA) for column-parallel readout circuits. The proposed ADC suppresses the random noise and enhances the resolution by embedding the conventional SA ADC with an integrator and decimation filter. In addition, the operating speed is increased through the two-step operations of coarse conversion with the proposed ADC and fine conversion with the embedded SA ADC. A residue fitting method is adopted to adjust the residue voltage to the fine conversion range after the coarse conversion. The proposed ADC with 12-bit resolution was fabricated using a 0.13 CMOS image sensor process with a pixel array that has an image format of 648 488 and a pixel size of . The measured results show a random noise of 108 , a dynamic range of 60.9 dB, a differential nonlinearity of 1.02/ 0.34 least significant bit (LSB), and an integral nonlinearity of 0.64/ 0.54 LSB.Index Terms-Column-parallel readout, incremental analog-todigital converter (ADC), successive approximation.

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A 12-bit 7 µW/channel 1 kHz/channel incremental ADC for biosensor interface circuits

Cited by 20 publications

References 6 publications

A Micro-Power Two-Step Incremental Analog-to-Digital Converter

A Micro-Power Two-Step Incremental Analog-to-Digital Converter

A high dynamic range analog-front-end IC for electrochemical amperometric and voltammetric sensors

A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits

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