16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Su, Jian‐Wei; Chou, Yen-Chi; Liu, Ruhui; Liu, Chun‐Jen; Lu, Pei-Jung; Wu, Ping-Chun; Chung, Yen-Lin; Hung, Li-Yang; Ren, Jin-Sheng; Pan, Tianlong; Li, Sih-Han; Chang, Shih-Chieh; Sheu, Shyh-Shyuan; Lo, Wei‐Chung; Wu, Chih-I; Si, Xin; Lo, Chung-Chuan; Liu, Ren-Shuo; Hsieh, Chih-Cheng; Tang, Kea-Tiong; Chang, Meng‐Fan

doi:10.1109/isscc42613.2021.9365984

Cited by 113 publications

(28 citation statements)

References 6 publications

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“…CIM integrated in the analog SRAM periphery is evaluated in [65] on a simulated 65nm process, reporting 4.9x system energy efficiency and 2.4x throughput improvement compared to digital processing. A 384kb SRAM-based 8b precision CIM in 28nm [66] is demonstrated to have 28% area overhead compared to a pure SRAM array while achieving up to 22.75TOPS/W throughput.…”

Section: In-memory Computingmentioning

confidence: 99%

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Jokic¹,

Azarkhish²,

Bonetti³

et al. 2022

ACM Trans. Embed. Comput. Syst.

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Implementing embedded neural network processing at the edge requires efficient hardware acceleration that combines high computational throughput with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly being adapted to support the improved functionalities. Hardware designers can refer to a myriad of accelerator implementations in the literature to evaluate and compare hardware design choices. However, the sheer number of publications and their diverse optimization directions hinder an effective assessment. Existing surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effects of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. In contrast to previous surveys, this work provides a quantitative overview of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. The list of optimizations and their quantitative effects are presented as a construction kit, allowing to assess the design choices for each building block individually. Reported optimizations range from up to 10’000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators.

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Section: In-memory Computingmentioning

confidence: 99%

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Jokic¹,

Azarkhish²,

Bonetti³

et al. 2022

ACM Trans. Embed. Comput. Syst.

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“…3 (a), discharges or maintains the CBL voltage state. Please note that 8 CBL capacitances (CCBL[0], … , CCBL [7]) mean MSB 1 bit (X [3]) representing 23 value, 4 CBL capacitances (CCBL [8], … , CCBL[11]) show X [2] representing 22 value, 2 CBL capacitances (CCBL[12], CCBL[13]) mean X [1] showing 21 value, and an CBL capacitance (CCBL[14]) represents LSB (X[0]), which is illustrated in Fig. 3(a).…”

Section: The 4-bit Dac and Its Mac Operation Using Bl Charge-sharingmentioning

confidence: 99%

“…Here, the number of the charged capacitances among 16 CBL's (CCBL[0], … ,CCBL[15]) represents the input activations values of X[3:0]. For example, when the 4-bit input is '1000(2)', the voltage levels of 8 CBL capacitances (CCBL[0], … , CCBL [7]) are discharged, and the rest of the capacitances (CCBL [8], … ,CCBL[15]) maintain the precharged state. The capacitances representing different digits are separated using the switch denoted as PGDAC of Type B peripheral circuit shown in Fig.…”

Section: The 4-bit Dac and Its Mac Operation Using Bl Charge-sharingmentioning

confidence: 99%

“…Then, based on the MSB data, we can determine whether the next 3-bit flash ADC sampling applies to the lower pMAC range (from 0 to 63) or the upper pMAC range (from 64 to 127). When the MSB is '0', the next 3-bit flash ADC sampling occurs on the lower pMAC range (from 0 to 63) using ABLREF [1] ~ ABLREF [7]. Otherwise, it is on the upper pMAC range (from 64 to 127) using ABLREF[9] ~ ABLREF [15].…”

Section: Bit-line Charge-sharing Based Adc Operationmentioning

confidence: 99%

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A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing

Kim

Lee

Park

2022

Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design

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This paper presents a low cost PMOS-based 8T (P-8T) SRAM Compute-In-Memory (CIM) architecture that efficiently performs the multiply-accumulate (MAC) operations between 4-bit input activations and 8-bit weights. First, bit-line (BL) chargesharing technique is employed to design the low-cost and reliable digital-to-analog conversion of 4-bit input activations in the proposed SRAM CIM, where the charge domain analog computing provides variation tolerant and linear MAC outputs. The 16 local arrays are also effectively exploited to implement the analog multiplication unit (AMU) that simultaneously produces 16 multiplication results between 4-bit input activations and 1-bit weights. For the hardware cost reduction of analog-to-digital converter (ADC) without sacrificing DNN accuracy, hardware aware system simulations are performed to decide the ADC bitresolutions and the number of activated rows in the proposed CIM macro. In addition, for the ADC operation, the AMU-based reference columns are utilized for generating ADC reference voltages, with which low-cost 4-bit coarse-fine flash ADC has been designed. The 256×80 P-8T SRAM CIM macro implementation using 28nm CMOS process shows that the proposed CIM shows the accuracies of 91.46% and 66.67% with CIFAR-10 and CIFAR-100 dataset, respectively, with the energy efficiency of 50.07-TOPS/W.

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“…Many studies have implemented PIM based on static random-access memory (SRAM) due to its logic compatibility and high operation speed [1][2][3][4][5][6][7]. However, SRAM-based PIMs have the limitations of low bit density and large silicon area [1,2].…”

Section: Introductionmentioning

confidence: 99%

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

Kim

Park

2022

Sensors

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This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell with a pseudo-static leakage compensation that maintains stored data without charge loss issue. Hence, the PS-GC can offer unlimited retention time in the same manner as static RAM (SRAM). Due to the extended retention time, bulky capacitors in conventional eDRAM are no longer needed, thereby, improving the area efficiency of eDRAM-based analog PIMs. The active leakage compensation of the PS-GC can effectively hold stored data even in a deep-submicron process that show significant leakage current. Therefore, the PS-GC can accelerate write-access time and read-access time without concern of increased leakage current. The proposed gain cell and its 64 × 64 eDRAM macro were implemented in a 28 nm CMOS process. The bitcell of the proposed gain cell has 0.79- and 0.58-times the area of those of 6T SRAM and 8T STAM, respectively. The post-layout simulation results demonstrate that the eDRAM maintains the pseudo-static operation with unlimited retention time successfully under wide range variations of process, voltage and temperature. At the operating frequency of 667 MHz, the eDRAM macro achieved an operating voltage range from 0.9 to 1.2 V and operating temperature range from −25 to 85 °C regardless of the process variation. The post-layout simulated write-access time and read-access time were below 0.3 ns at an operating temperature of 85 °C. The PS-GC consumes a static power of 2.2 nW/bit at an operating temperature of 25 °C.

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16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Cited by 113 publications

References 6 publications

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

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