16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving −70.8dBc ACPR in a 20MHz channel at 5.2GHz

Erdmann, Christophe; Cullen, Edward; Brouard, Damien; Pelliconi, Roberto; Verbruggen, Bob; McGrath, John; Collins, Diarmuid; Torre, Marites De La; Gay, Pierrick; Lynch, Patrick; Lim, Peng; Collins, Anthony; Farley, Brendan

doi:10.1109/isscc.2017.7870370

Cited by 30 publications

(34 citation statements)

References 3 publications

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“…Since the proposed RF DAC is very compact in size, it can replace high-speed serial data link block in a digital ASIC meaning that basically the monolithic integration of the RF DAC comes with no die-area increase for the digital ASIC in fully digital beamforming 5G architectures. The proposed work is compared against some of the recent state-of-the-art RF DACs [1,4,11]. These RF DACs are implemented in current-steering architecture.…”

Section: Comparison and Conclusionmentioning

confidence: 99%

“…Finite output impedance of the unit element current sources causes harmonic distortion and mismatch between the unit element current sources causes timing and amplitude inaccuracy and hence harmonic distortion. To mitigate the finite output impedance of current-steering architecture, works in [1,4,11] utilize the bleeding current source technique proposed in [10], making the output impedance of the DAC independent of the input code. Moreover in a current-steering structure the mismatch can happen between unit current sources and also between the switches.…”

Section: Comparison and Conclusionmentioning

confidence: 99%

“…Using the aforementioned techniques, the work in [11] achieves IM3 better than 70 dBc up to 4.5 GHz output frequency and the work in [4] achieved IM3 better than 65 dBc up to 6.8 GHz output frequency, both in 16 nm CMOS technology. The proposed solution in this work has shown in simulations to be able to achieve better than 70 dBc IM3 in output frequencies up to 10 GHz in 22 nm CMOS technology without any calibration, trimming or compensation method.…”

Section: Comparison and Conclusionmentioning

confidence: 99%

See 2 more Smart Citations

A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

Sadeghifar

Bengtsson

Wikner

2019

Analog Integr Circ Sig Process

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As the number of antenna elements increases in massive multiple-input multiple-output-based radios such as fifth generation mobile technology (5G), designing true multi-band base-station transmitter, with efficient physical size, power consumption and cost in emerging cellular frequency bands up to 10 GHz, is becoming a challenge. This demands a hard integration of radio components, particularly the radio's digital application-specific integrated circuits (ASIC) with high performance multi-band data converters. In this work, a novel radio frequency digital-to-analog converter (RF DAC) solution is presented, that is also capable of monolithic integration into today's digital ASIC due to its digital-in-nature architecture. A voltage-mode conversion method is used as output stage, and configurable mixing logic is employed in the data path to create a higher frequency lobe and utilize the output signal in the first or the second Nyquist zone. This 12-bit RF DAC is designed in a 22 nm FDSOI CMOS process, and shows excellent linearity performance for output frequencies up to 10 GHz, with no calibration and no trimming techniques. The achieved linearity performance is able to fulfill the high requirements of 5G base-station transmitters. Extensive Monte-Carlo analysis is performed to demonstrate the performance reliability over mismatch and process variation in the chosen technology.

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Section: Comparison and Conclusionmentioning

confidence: 99%

Section: Comparison and Conclusionmentioning

confidence: 99%

Section: Comparison and Conclusionmentioning

confidence: 99%

See 1 more Smart Citation

A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

Sadeghifar

Bengtsson

Wikner

2019

Analog Integr Circ Sig Process

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show abstract

“…In an attempt to "digitalize" the IQ transceiver, direct-digital-to-RF transmitters have been suggested [73,60,36,4,6,5,71,3,19,39,40,100,81,107].…”

Section: Direct-digital-to-rf Transmittermentioning

confidence: 99%

“…To this end, high performance data converters are highly demanded in order to fulfill the wireless infrastructure requirements with high output bandwidth to cover multiple frequency bands, and in the same time, compatible with digital integration [78,63,76,39,79,59].…”

Section: Introductionmentioning

confidence: 99%

Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters

Sadeghifar

2019

Linköping Studies in Science and Technology. Dissertations

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The network latency in fifth generation mobile technology (5G) will be around one millisecond which is much lower than in 4G technology. This significantly faster response time together with higher information capacity and ultra-reliable communication in 5G technology will pave the way for future innovations in a smart and connected society. This new 5G network should be built on a reasonable wireless infrastructure and 5G radio base stations that can be vastly deployed. That is, while the electrical specification of a radio base station in 5G should be met in order to have the network functioning, the size, weight and power consumption of the radio system should be optimized to be able to commercially deploy these radios in a huge network. Last but not least I would like to especially thank my soulmate and my love Hoda. Without all your help, your devotion and patience, I would not be able to complete this work. Therefore, I dedicate this work to you.

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A 4–5.2 GHz PLL with 74.8 fs RMS jitter in 28 nm for RF Sampling Transceiver application

Zhao,

Zhang,

Zhang

et al. 2023

Micro & Optical Tech Letters

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This paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246.

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16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving −70.8dBc ACPR in a 20MHz channel at 5.2GHz

Cited by 30 publications

References 3 publications

A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters

Studies on Selected Topics in Radio Frequency Digital-to-Analog Converters

A 4–5.2 GHz PLL with 74.8 fs RMS jitter in 28 nm for RF Sampling Transceiver application

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