2023 IEEE International Solid- State Circuits Conference (ISSCC) 2023
DOI: 10.1109/isscc42615.2023.10067352
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16.5 DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching

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Cited by 21 publications
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“…4(f-i) shows the 1T-1C/2T-1C/3T-1C/4T-2C eDRAM cells from [28,29,30,31], respectively. The above eDRAM cells store the weights on the internal capacitor and perform similar computations like SRAM cells in currentbased [28,29,30] or charge-based [31] approaches. Its dynamic feature reduces the transistor counts and enables multi-bit storage on the dynamic node [30,6].…”
Section: Volume mentioning
confidence: 99%
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“…4(f-i) shows the 1T-1C/2T-1C/3T-1C/4T-2C eDRAM cells from [28,29,30,31], respectively. The above eDRAM cells store the weights on the internal capacitor and perform similar computations like SRAM cells in currentbased [28,29,30] or charge-based [31] approaches. Its dynamic feature reduces the transistor counts and enables multi-bit storage on the dynamic node [30,6].…”
Section: Volume mentioning
confidence: 99%
“…FIGURE 4. Different types of volatile CIM cells: (a) 6T SRAM cell [4], (b) 8T SRAM cell [25], (c) 8T-1C SRAM cell [26], (d) 9T-1C SRAM cell [8], (e) 10T-2C SRAM cell [27], (f) 1T-1C eDRAM cell [28], (g) 2T-1C eDRAM cell [29], (h) 3T-1C eDRAM cell[30] and (i) 4T-2C eDRAM cell [31]. …”
mentioning
confidence: 99%