2017 IEEE International Solid-State Circuits Conference (ISSCC) 2017
DOI: 10.1109/isscc.2017.7870373
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16.6 A 10b DC-to-20GHz multiple-return-to-zero DAC with >48dB SFDR

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Cited by 2 publications
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“…GHz. Similarly, in [10] a f out of 20 GHz is obtained when operating with an f s of 3.35 GHz. Yet, f out close to f s have been reported in CMOS CS DACs with the utilization of the mixing-mode technique [30], [44].…”
Section: Comparison Of High-speed Dacsmentioning
confidence: 84%
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“…GHz. Similarly, in [10] a f out of 20 GHz is obtained when operating with an f s of 3.35 GHz. Yet, f out close to f s have been reported in CMOS CS DACs with the utilization of the mixing-mode technique [30], [44].…”
Section: Comparison Of High-speed Dacsmentioning
confidence: 84%
“…1.1 [9], where it is observed that the energy consumption has been declining with time. Al- ternatively, hybrid DAC topologies and architectures have been proposed for high-speed, e.g., resistive R-2R ladder with CS DACs as well as the integration of both Nyquist and Σ∆ DACs to balance between sampling speed and resolution [10], [11]. On the other hand, improvements in CS DAC's performance have come at a cost of increased power consumption and complexity in the design.…”
Section: Cmos Technology Has Become the Preferred Option To Obtain En...mentioning
confidence: 99%
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