16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs&lt;inf&gt;rms&lt;/inf&gt; Jitter in 65nm LP CMOS

Grimaldi, Luigi M. E.; Bertulessi, Luca; Karman, Saleh; Cherniak, Dmytro; Garghetti, Alessandro; Samori, Carlo; Lacaita, A.L.; Levantino, Salvatore

doi:10.1109/isscc.2019.8662411

Cited by 13 publications

(5 citation statements)

References 6 publications

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“…The standard metrics for PLL performance quality are ℒnorm [16], FoM [1], and FoMJRP [21] described as follows: 20 log( ) 10 log( ) ISSCC'19 [22] ISSCC'20 [23] TMTT'17 [24] ISSCC'16 [25] TMTT'20 [26] ISSCC'19 [27] This work…”

Section: Measurement Results and Discussionmentioning

confidence: 99%

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fs_rms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

Liang

Boon

2022

IEEE Trans. Microwave Theory Techn.

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The high phase noise of CMOS millimeterwave oscillators has encouraged the adoption of wide loop bandwidth for an integer-N phase-locked loop (PLL). This paper proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the trade-off between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection as well as lock detection. Implemented in 40 nm CMOS technology, the proposed PLL shows a −75 dBc reference spur, -101.5 dBc/Hz phase noise at 1 MHz offset, and a minimum integrated jitter of 121.9 fsrms (10 k -100 MHz) at 38.2 GHz, with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.

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Section: Measurement Results and Discussionmentioning

confidence: 99%

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fs_rms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

Liang

Boon

2022

IEEE Trans. Microwave Theory Techn.

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“…Therefore, SSPLL techniques are more frequently adopted in LC-based PLLs over ringbased PLLs where the in-band noise is less important due to the dominant ring-VCO noise. For example, the survey shows 17 LC-based SSPLLs [4], [36], [46]- [47], [58]- [59], [106]- [107], [115], [118]- [119], [123]- [124], [126]- [127], [133], [140] but only 4 ring-based SSPLLs [11], [91], [120], [141]. On the other hand, because of the nature of the SSPD, a SSPLL does not distinguish harmonic frequencies, so it needs a separate frequency tracking loop.…”

Section: B Sub-sampling Pll (Sspll)mentioning

confidence: 99%

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

Bae

2022

IEEE Access

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A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most powerful indicator to compare and to normalize performance of different PLL designs. Simply, the conventional FOM is based on the jitter-power trade-off. With a few assumptions, theoretically, it provides a fair comparison. However, as the PLL design techniques have advanced, the assumptions have started breaking. Also, it misses performance impacts from some other important factors other than the jitter and the power. As a result, it is expected that the performance comparison with the conventional FOM is not fair enough for some cases. This work reviews the state-of-the-art PLL design techniques and investigates how those techniques conflict with the assumptions of the conventional FOM. In addition, alternate FOMs which complement the conventional FOM are discussed. To capture complex cross-correlation between various factors, the proposed methodology is to find a correlation between the conventional FOM and other factors from extensive performance surveys, along with quantitative analyses.

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“…Hence, the frequency is locked even with the ODZ detector activated. Conventionally, an FLL is used to monitor the frequency error in the background [5] and can be used for detecting this error. However, an FLL consumes a significant amount of power due to its high operating frequency.…”

Section: B Proposed Duty-cycled Fllmentioning

confidence: 99%

“…Fig. 1(b) shows another popular architecture for low-power design, namely the dividerless architecture [5]- [7]. It directly samples and compares the DCO clock (CKV) with the reference clock.…”

mentioning

confidence: 99%

A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS

Liu

Shirane

Okada

et al. 2019

IEEE J. Solid-State Circuits

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This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves a 265-µW ultra-lowpower operation. The proposed switching feedback can seamlessly change the DPLL from sampling operation to sub-sampling operation without disturbing the phase-locked state of the DPLL to reduce the number of building blocks that works at the oscillator frequency, leading to significant power reduction. With the reduced number of high-frequency circuits, scaling the reference frequency is fully used to reduce the power consumption of the DPLL. Together with an out-of-dead-zone detector and a duty-cycled frequency-locked loop running in the background, the switching feedback achieves robust frequency and phase acquisition at start-up and helps the sub-sampling PLL recover when large phase and frequency disturbances occur. A transformer-based stacked-g m oscillator is proposed to minimize the power consumption while providing the sufficient swing to drive the subsequent stages. A truncated constant-slope digital-to-time converter is proposed to improve the power efficiency while retaining good linearity. The proposed fractional-N DPLL consumes only 265 µW while achieving an integrated jitter of 2.8 ps and a worst case fractional spur of −52 dBc, which corresponds to a figure of merit (FOM) of −237 dB.

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16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs<inf>rms</inf> Jitter in 65nm LP CMOS

Cited by 13 publications

References 6 publications

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fs_rms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fs_rms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS

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16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs<inf>rms</inf> Jitter in 65nm LP CMOS

Cited by 13 publications

References 6 publications

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fsrms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fsrms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS

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A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fs_rms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fs_rms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector