A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fs_rms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector

Abstract

The high phase noise of CMOS millimeterwave oscillators has encouraged the adoption of wide loop bandwidth for an integer-N phase-locked loop (PLL). This paper proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the trade-off between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection as well as lock detection. Implemented in 40 nm CMOS technology, the proposed PLL shows a −75 dBc reference spur, -101.5 dBc/Hz phase noise at 1 MHz offset, and a minimum integrated jitter of 121.9 fsrms (10 k -100 MHz) at 38.2 GHz, with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB.

A Simplified Gm − C Filter Technique for Reference Spur Reduction in Phase-Locked Loop

“…Several methods of spur reduction for PLLs have been published. In [3][4][5][6][7][8][9][10][11][12][13], the authors utilized the higher-order loop filter to achieve an acceptable spur level (<−65 dBc). However, a higher-order loop filter affects the PLL phase margin which might make the system unstable.…”

“…the input impedance is equal to Z in = sC L g ma .g mb (10) Therefore, the gyrator, in this case, behaves as an inductor with an equivalent inductance of L eq . The equivalent inductance is given by (11).…”

“…The received signal is weak (≈−130 dB), hence a high-sensitivity receiver is required for proper reception because IRNSS receivers are designed for critical applications like realtime monitoring and precise location positioning. Any receiver's sensitivity depends on the local oscillator's (LO) phase noise (PN), spectrum purity, and low spurs [3][4][5][6][7][8][9][10][11][12][13], which makes the design of the phase-locked loop (PLL) complicated [1,14]. In applications of transceivers, it is important to maintain a pure, single-tone spectrum, without unwanted tones to avert a corruption of required data.…”

Review of recent progress on solid‐state millimeter‐wave and terahertz signal sources

“…Moreover, K VCO affects the PLL settling time and the loop stability since it appears in the PLL open-loop transfer function. 88 In general, attaining a completely linear tuning curve over the whole VCO FTR is difficult as the varactor capacitance varies in a nonlinear manner. Such a nonlinear characteristic possibly degrades the system performance.…”

A 21.8–41.6-GHz Low Jitter and High FoM$_{\bm{j}}$ Fast-Locking Subsampling PLL With Dead Zone Automatic Controller

“…In the sacrifice of large chip area, this kind of PLL still faces the challenge of low phase noise at mm-wave due to the large division ratio. Recently, different types of mm-wave PLLs with low phase noise are reported [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20]. The mm-wave PLLs utilizing high-frequency crystal and large loop bandwidth have demonstrated low phase noise [15], [16], [17].…”