2016 IEEE International Solid-State Circuits Conference (ISSCC) 2016
DOI: 10.1109/isscc.2016.7418029
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17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization

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Cited by 34 publications
(6 citation statements)
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“…The evaluation was carried out over 14 nm of node and was tested with respect to current-voltage charecteristics. The study has also investigated about the trends of heat dissipation from the 14nm node to find the temperature reduction capability of 325 K. Study in similar direction was also carried out by Song et al [21] Ansari et al [22] have presented an elaborated study of design improvement of SRAM cells with 7 transistors. The author has considered a simulation-based study with HSPICE using multiple number of transistor (20,16,14, 10, 7 nm).…”
Section: Existing Techniquesmentioning
confidence: 93%
“…The evaluation was carried out over 14 nm of node and was tested with respect to current-voltage charecteristics. The study has also investigated about the trends of heat dissipation from the 14nm node to find the temperature reduction capability of 325 K. Study in similar direction was also carried out by Song et al [21] Ansari et al [22] have presented an elaborated study of design improvement of SRAM cells with 7 transistors. The author has considered a simulation-based study with HSPICE using multiple number of transistor (20,16,14, 10, 7 nm).…”
Section: Existing Techniquesmentioning
confidence: 93%
“…Hence, the scaling boosters of SRAM bitcell area with evolving technology from fin, nanosheet (NS), forksheet (FS) [2], and complementary (C) FETs [3][4][5] are summarized in this paper. The HD 6T SRAM bitcell area scaling benchmark between different companies [6][7][8][9][10][11][12][13] and corresponding imec's key design rules, contacted poly pitch (CPP) and metal pitch (MP), are summarized in Figure 1. As migrating from Fin to NS technology, the NSFET SRAM offers superior effective width per footprint and channel controllability.…”
Section: Introductionmentioning
confidence: 99%
“…1(b). For improving writability, the negative bitline (NBL) [5], [7], [10], [12], [14]- [16], transient cell supply collapse (TVC) [4], [8], [13]- [17], transient cell ground bump (TGB) [18]- [20], or wordline overdrive (WLOD) WA [9], [12], [21], [22] is used. Although the various RA and WA techniques reduce the V MIN , reducing the energy consumed in the assist circuit is still challenging.…”
Section: Introductionmentioning
confidence: 99%