A single-inductor, dual-input, and dual-output boost converter harvesting thermal and solar energy with a novel time-multiplexing maximum power point tracking (MPPT) algorithm is proposed in this paper. The proposed boost converter harvests energy from thermoelectric generator (TEG) and photovoltaic cell (PV cell) and applies the harvested power to the load and battery. The proposed MPPT algorithm controls the effective frequency of energy harvesting from TEG and PV cell by time multiplexing. As a result, the MPPT can be achieved using a single system clock frequency. The reduced number of required system clock frequencies can leads to power and area savings owing to the reduced clock generation circuits. The proposed boost converter is designed using 65 nm CMOS process technology and evaluated using the HSPICE simulation. The peak power conversion efficiency of the proposed boost converter is 78%.

No abstract

The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an average-8T SRAM architecture, a full-swing local bitline (BL) that is connected to the gate of the read buffer can be achieved with a boosted wordline (WL) voltage. However, in the case of an average-8T SRAM based on an advanced technology, such as a 22-nm FinFET technology, where the variation in threshold voltage is large, the boosted WL voltage cannot be used, because it degrades the read stability of the SRAM. Thus, a full-swing local BL cannot be achieved, and the gate of the read buffer cannot be driven by the full supply voltage (V DD ), resulting in a considerably large read delay. To overcome the above disadvantage, in this paper, a differential SRAM architecture with a full-swing local BL is proposed. In the proposed SRAM architecture, full swing of the local BL is ensured by the use of cross-coupled pMOSs, and the gate of the read buffer is driven by a full V DD , without the need for the boosted WL voltage. Various configurations of the proposed SRAM architecture, which stores multiple bits, are analyzed in terms of the minimum operating voltage and area per bit. The proposed SRAM that stores four bits in one block can achieve a minimum voltage of 0.42 V and a read delay that is 62.6 times lesser than that of the average-8T SRAM based on the 22-nm FinFET technology.Index Terms-Bit-interleaving, FinFET, low-voltage operation, static random access memory (SRAM). 1063-8210

No abstract

Recently, spiking neural networks have gained attention owing to their energy efficiency. Allto-all spike-time dependent plasticity is a popular learning algorithm for spiking neural networks because it is suitable for nondifferentiable spike event-based learning and requires fewer computations than backpropagation-based algorithms. However, the hardware implementation of all-to-all spike-time dependent plasticity is limited by the large storage area required for spike history and large energy consumption caused by frequent memory access. We propose a time-step scaled spike-time dependent plasticity to reduce the storage area required for spike history by reducing the area of the spike-time dependent plasticity learning circuit by 60% and a post-neuron spike-referred spike-time dependent plasticity to reduce the energy consumption by 99.1% by efficiently accessing the memory while learning. The accuracy of Modified National Institute of Standards and Technology image classification degraded by less than 2% when both time-step scaled spike-time dependent plasticity and post-neuron spike-referred spike-time dependent plasticity were applied. Thus, the proposed hardware-friendly spike-time dependent plasticity algorithms make all-to-all spike-time dependent plasticity implementable in more compact areas while reducing energy consumption and experiencing insignificant accuracy degradation. INDEX TERMS Spike-time dependent plasticity (STDP), Time-step scaled STDP (TS-STDP), Postneuron spike-referred STDP (PR-STDP), Spiking neural network (SNN) Wij Learning neuron Synaptic weight Off-chip On-chip Pre-neuron spike Post-neuron spike ... ... FIGURE 1. Concept of SNN and its structure.