Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

Kang, Kyoman; Jeong, Hong; Yang, Yong Sook; Park, Juhyun; Kim, Kiryong; Jung, Seong‐Ook

doi:10.1109/tvlsi.2015.2450500

Cited by 19 publications

(4 citation statements)

References 14 publications

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“…Increasing transistor performance variation with dimensional scaling is one hurdle to getting a high enough SRAM yield [11,12]. Moreover, the friction between read and write stability is the main issue with 6T SRAM cells [13,14]. Many researchers have conducted investigations on the device and circuit level to solve the problems faced in SRAM cells.…”

Section: Introductionmentioning

confidence: 99%

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Singh,

Chaudhary,

Dewan

et al. 2024

Eng. Res. Express

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Junctionless FinFET devices are a substitute for conventional FinFET devices due to their less short channel effects and easy manufacturing at sub 22-nm technology node. The manuscript presents an 8T-SRAM cell based on tri-gate junctionless FinFET technology. The FinFET device is designed with source/drain of Si material and the channel as a stack of Si − Si0.75Ge0.25 − Si. The proposed SRAM cell structure consists of a CMOS inverter with stacked p-FinFETs, improving its performance in terms of noise margin and leakage power consumption. The manuscript investigates the variation of Static Noise Margin (SNM), leakage power dissipation and delay with supply voltage to analyze the sub-threshold operation of SRAM cell. The results reveal that the cascaded p-FinFETs minimize the leakage current owing to the stack eﬀect, resulting in improved noise margin and lower leakage power. The stacked p-FinFET devices based SRAM cell achieves 1.11x read noise margin, 1.11x hold noise margin, -1.08x write noise margin and 57.1% less leakage power compared to conventional SRAM cell at 1.0 V. However, it exhibits more delay due to increased resistance and capacitance of the cascaded transistors. The process variation analysis is also performed to investigate the SNM distribution using monte-carlo simulation by taking 10,000 samples. The results indicate that the SRAM cell structures provide higher than 6σ yield at range of supply voltages.

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Section: Introductionmentioning

confidence: 99%

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Singh,

Chaudhary,

Dewan

et al. 2024

Eng. Res. Express

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“…However, the local and global bit-lines cannot achieve full swing due to less write ability, slow operation, and high-power consumption. The full-swing local bit-line SRAM architecture [18] was proposed but still poor write ability because two cascade transistors controlled the bit cell. The 10 T SRAM [19] stack pull-down transistors for a cross-coupled inverter with VGND technology was proposed to change the write path, but the write ability is still inefficient.…”

Section: Introductionmentioning

confidence: 99%

Stable Local Bit-Line 6 T SRAM Architecture Design for Low-Voltage Operation and Access Enhancement

et al. 2021

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To incur the memory interface and faster access of static RAM for near-threshold operation, a stable local bit-line static random-access memory (SRAM) architecture has been proposed along with the low-voltage pre-charged and negative local bit-line (NLBL) scheme. In addition to the low-voltage pre-charged and NLBL scheme being operated by the write bit-line column to work out for the write half-select condition. The proposed local bit-line SRAM design reduces variations and enhances the read stability, the write capacity, prevents the bit-line leakage current, and the designed pre-charged circuit has achieved an optimal pre-charge voltage during the near-threshold operation. Compared to the conventional 6 T SRAM design, the optimal pre-charge voltage has been improved up to 15% for the read static noise margin (RSNM) and the write delay enriched up to 22% for the proposed NLBL SRAM design which is energy-efficient. At 400 mV supply voltage and 25 MHz operating frequency, the read and write energy consumption is 0.22 pJ and 0.23 pJ respectively. After comparing with the related works, the access average energy (AAE) is lower than in other works. The overall performance for the proposed local bit-line SRAM has achieved the highest figure of merit (FoM). The designed architecture has been implemented based on the 1-Kb SRAM macros and TSMC−40 nm GP process technology.

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“…Various SRAM topologies have been proposed by many researchers with different circuit-level techniques to improve various performance metrics [8][9][10][11][12]. A differential 22-nm FinFET 8T SRAM cell design with a full-swing local bit line using cross-coupled PMOS with reduced read delay and power has been presented [13]. Capacitive-coupling (CC) between write word line and bit line for write word line boosting has been used to achieve a reduction in VMIN in 22-nm 8T SRAM [14].…”

Section: Introductionmentioning

confidence: 99%

Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability

Duari

Birla

Singh³

2020

JICS

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Static Random-Access Memory cells with ultralow leakage and superior stability are the primary choice of embedded memories in contemporary smart devices. This paper presents a novel 8T SRAM cell with reduced leakage and improved stability. The proposed SRAM cell uses a stacking effect to reduce leakage and transmission gate as an access transistor to enhance stability. The performance of the proposed 8T SRAM cell with a stacked transistor has been analyzed based on the power consumption and static noise margin (RSNM, HSNM, and WSNM). The power consumption in the case of FinFET based 8T cell is found to be 572 pW at 22 nm technology node, which is reduced by a factor nearly as compared to that of CMOS based 8T cell. Further, in the case of FinFET based novel 8T SRAM cell at 22 nm technology node, the power consumption is found to be reduced by a factor of as compared to that of FinFET based conventional 6T SRAM cell. WSNM, HSNM, and RSNM of the 8T SRAM cell designed with FinFET logic are observed as 240 mV, 370 mV, and 120 mV respectively at 0.9 V supply voltage. When comparing with conventional 6T FinFET Cell, the proposed Cell shows 20%, 5.11%, and 7% improvement in WSNM, HSNM, and RSNM, respectively. The sensitivity of SNM with temperature variation is also analyzed and reported. Further, the results obtained confirm the robustness of the proposed SRAM cells as compared to several recent works.

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Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

Cited by 19 publications

References 14 publications

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

Stable Local Bit-Line 6 T SRAM Architecture Design for Low-Voltage Operation and Access Enhancement

Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability

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