In the present time, great emphasis has been given to the design of low-power and high performance memory circuits. As an SRAM is a critical component in both high-performance processors and hand-held portable devices. So the ever-increasing levels of on-chip integration of SRAM, offers serious design challenges in terms of power requirement and cell stability. There is a significant increase in the sub-threshold leakage due to its exponential relation to the threshold voltage, and gate leakage due to the reducing gate-oxide thickness. In order to minimize the leakage current, the supply voltage is reduced drastically which reduces the threshold voltage of the cell.This reduces the threshold voltage of the cell which results in reduction of the Static Noise Margin (SNM) of the cell and affect the data stability of the cell, seriously. In this work, the solutions for theses two problems, in the conventional 6T SRAM Cell has been explored.

This article aims to provide a wide comparative analysis of different SRAM cells in 7nm FinFET Technology. Due to various limitations of the CMOS device in nanotechnology, FinFET is one of the trending choices for memory designers which can improve the stability and minimize the Short Channel Effects of the CMOS. Here, performance metrics of these SRAM cells like the stability, access time, power have been measured at a supply voltage range of 0.2 V to 0.5 V. The layout of the existing cells has been designed and compared in which the ST12T consumes the maximum area. The simulated results inferred that the ST11T SRAM cell offers the highest RSNM and the minimum dynamic and leakage power amongst all the SRAM cells. Moreover, ST12T SRAM cell has the highest WSNM in comparison to other SRAM cells. An electrical quality metric has been utilized, which displays the superiority of the ST12T SRAM cell amongst all the considered SRAM cells in this article.

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