Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM

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This paper presents a robust low‐power 10T SRAM cell (RLP10T) with a novel read/write assist mechanism, improving both read static noise margin (RSNM) and write static noise margin (WSNM) simultaneously. To assess its relative strength, we compared the proposed cell with recently published SRAM cells such as WRE8T, 10T‐P1, HFBS10T, WALP11T, and SE11T in 16‐nm CMOS technology node. The RLP10T cell shows 3.55/1.07 times higher/lower RSNM compared to the WRE8T/WALP11T cell and offers at least 1.10 times higher WSNM. Due to the presence of three series‐connected transistors in its read path, which includes a strong pull‐down transistor, the proposed design shows 1.23 times shorter read delay (TRA) than that of 10T‐P1/HFBS10T cell. The proposed cell incurs a penalty of high write delay (TWA) due to its long write path. However, it exhibits the fourth (second)‐best read (write) power, attributed to its single‐ended structure and lower read (write) frequency. It also dissipates acceptable leakage power due to its single‐bitline structure and the presence of stacked transistors in its read path and pull‐down path of one of the inverters in the cell core. Subjected to the severe process, voltage, and temperature variations, the RLP10T cell offers at least 1.31/1.09/1.03 times lower variability in RSNM/WSNM/TRA at VDD = 0.7 V, at the cost of 1.22 times area overhead compared to the WRE8T cell.

α_{bitline}

is the bitline's switching activity factor,

C_{effective}

is the effective capacitance,

V_{DD}

is the operating power supply voltage, and

f_{italicread / italicwrite}

is the reading/writing frequency 36

P_{italicdynamic - italicread / italicwrite} goodbreak= α_{bitline} goodbreak\times C_{effective} goodbreak\times V_{DD}^{2} goodbreak\times f_{italicread / italicwrite} .

…”

Section: Simulation Setup and Resultsmentioning

confidence: 99%

Section: Leakage Power Dissipationmentioning

confidence: 99%

Improved read/write assist mechanism for 10‐transistor static random access memory cell

Abbasian

Gholipour

2022

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“…The gate width of a GNRFET device is calculated by Equation (1). The total width of the THA circuits can be calculated by Equation (7), in which m and Tr are the transistor count of the THA circuit and the abbreviation for the transistor, respectively. For CNTFET-based THA circuits, n tube = 5, T ox = 1.5 nm, Pitch = 20 nm.…”

Section: Inputs Outputsmentioning

confidence: 99%

“…However, as the technology scaling enters beyond 32 nm regime, CMOS devices face many serious problems such as increased leakage currents, difficulty with an increase in ON-current, large parametric variations, low reliability, increase in manufacturing cost, etc. [6][7][8][9][10] So, there is a need to look for different potential alternatives to CMOS. It is found that carbon nanotube field-effect transistors (CNTFET) and graphene nanoribbon field-effect transistors (GNRFET) have a higher power of switch, curves with more ideal voltage, and better mobility, consequently, they can be favorable replacements for CMOS.…”

mentioning

confidence: 99%

An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technology

Abbasian,

Orouji,

Taghipour Anvari

et al. 2023

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SummaryInternet‐of‐Things (IoTs)‐based embedded systems require energy‐efficient designs for long‐term operation. To achieve energy‐efficient designs, multiple‐valued logic (MVL) circuits and graphene nanoribbon field‐effect transistors (GNRFETs) are used instead of binary logic circuits and complementary metal‐oxide‐semiconductor (CMOS), respectively. This paper presents a novel ultra‐low power and energy‐efficient ternary Half‐Adder (THA) circuit based on unary operators, two power supplies (dual‐VDD), VDD and VDD/2, and two ternary 3:1 multiplexers in 32 nm GNRFET technology. The superiority of the proposed design are improvements between 2.86% and 60% in transistor count, between 86.12% and 97.15% in power consumption, and between 58.14% and 98.39% in power‐delay‐product (PDP) compared to existing THA circuits. Moreover, the proposed THA circuit is also implemented with 32 nm carbon nanotube field‐effect transistors (CNTFETs). Simulation results indicate that the proposed GNRFET‐based THA circuit increases delay by 1.74 × and reduces power/PDP by 89.41%/81.63% compared to its CNTFET‐based counterpart.

“…RSNM is a measure of the stability of an SRAM cell during the read operation, which is graphically measured by the read butterfly curves. It is the side length of the largest square that can be inserted inside the smallest wing of the read butterfly curves, 7,31,32 as shown in Figure 3. The FD8T is indeed the conventional 6T SRAM cell plus AND gate-based inverter to eliminate half-select issues.…”

Section: Read Stabilitymentioning

confidence: 99%

Design and investigation of stability‐ and power‐improved 11T SRAM cell for low‐power devices

Abbasian

Birla

Moslem

2022

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The modern system‐on‐chips require stable and low‐power SRAM cells due to technology scaling and limited sources of energy. Therefore, a stability‐ and power‐improved 11T SRAM cell is proposed in this study. The proposed cell core is composed of a strong cross‐coupled structure of a conventional inverter with a N‐type stacked transistor and a Schmitt‐trigger (ST) with a double channel‐length pull‐up network. This coupled with a separate read path enhances the read static noise margin (RSNM). Moreover, a feedback‐cutting N‐type transistor is placed inside the cell core to improve the write static noise margin (WSNM)/write margin (WM). Though the presence of stacked transistors in access paths increases read delay (TRA)/write delay (TWA), it reduces leakage. This metric further minimizes with the aid of a stacked structure of latch core and double channel‐length of pull‐up transistor in the ST inverter. The moderate read/write frequency and single‐ended structure of the suggested cell result in low dynamic power. Simulated results by using 16‐nm CMOS at VDD = 0.7 V show that the proposed cell has the second‐best RSNM/WSNM, which is 4.65/1.44 times higher than that of the fully differential 8T (FD8T) cell, as the basic cell. Moreover, it reduces leakage power by at least 2.01 times and consumes moderate read/write power, nearly 1.44/1.81 times lower than that of FD8T cell, at the cost of 1.61 times area overhead. The proposed cell can eliminate read/write‐half‐select‐disturbance issues to support bit‐interleaving architecture to increase soft error immunity.