SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation

Cho, Keonhee; Park, Juhyun; Kim, Kiryong; Oh, Tae Woo; Jung, Seong‐Ook

doi:10.1109/tcsii.2021.3103916

Cited by 4 publications

(10 citation statements)

References 14 publications

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“…As shown in Figure 3(a), the Q-node of the memory cell is tripped at a swept word line (WL) voltage range of 0.46 to 0.61 V for a supply voltage VDD of 1 V. The mean write trip points (WTP) levels are decreased with scaling the supply voltage, which indicates scaling the supply voltage makes the cell unstable and quickly accepts the changes in bit (BIT) and bit bar (BITB) lines. So, the Q-node of a memory cell is tripped at a sweep WL voltage range of 0.33 to 0.39 V for a scaled supply voltage VDD of 0.6 V. So writeability is improved by scaling the SRAM cell's supply voltage, which is done by the CCS write-assist circuit [5]. The WTP voltage occurrence levels are plotted using Monte Carlo simulation, and it was observed that all strong cell samples with high VDD occurred on the right side (at maximum trip voltage levels).…”

Section: Capacitive Charge Sharing Write-assist Circuitmentioning

confidence: 99%

“…Tran-NBL write-assist circuit, shown in Figure 4(a), can improve the write performance with the help of two charging capacitors (CRBOOST and CLBOOST). One end of these capacitors is connected to the BIT line and write word line-B (WWLB) of the 9T SRAM cell, and the opposite end of the capacitors is connected to the control input 'BIT_EN', as shown in Figures 4(b) and (c) [5]. Figure 4(d) depicts the timing diagram for the circuit functioning.…”

Section: Tran-negative Bit Line (T-nbl) Write-assist Circuitmentioning

confidence: 99%

“…Write-ability can be improved by modifying the memory architecture with assist circuits [3], [4]. This paper is written in the following manner: section 2 describes the capacitive charge sharing (CCS) [5] and Tran-NBL circuits that assist [6] in increasing the write-ability. The proposed write-assist driver circuit design for the 9T-ST SRAM cell is presented in section 3.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

Chokkakula

Noorbasha

Murthy

2023

IJECE

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<span lang="EN-US">This paper presents a reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuit for the 9T Schmitt trigger-based static random-access memory (SRAM) cell (9T-ST), significantly improving write performance for real-time memory applications. In deep sub-micron technology, increasing device parameter deviations significantly reduce SRAM cells' write-ability. The proposed RNBLCS write-assist driver for 9T-ST SRAM cell has 0.84×, 0.48×, 0.27× optimized write access delay and 1.05×, 1.08×, 1.19× improvement in write static noise margin (WSNM), 1.05×, 1.13×, and 1.39× improvement in write margin (WM), 0.96×, 0.89× and 0.72× minimum write trip-point (WTP) from transient-negative bit line (Tran-NBL), capacitive charge sharing (CCS), and conventional write circuits respectively. The proposed RNBLCS is functionally verified using a synopsys custom compiler with a 16 nm BSIM4 model card for bulk complementary metal-oxide semiconductor (</span><span lang="EN-US">CMOS).</span>

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Section: Capacitive Charge Sharing Write-assist Circuitmentioning

confidence: 99%

Section: Tran-negative Bit Line (T-nbl) Write-assist Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

Chokkakula

Noorbasha

Murthy

2023

IJECE

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“…Write-ability performance analysis of memory cell through the "WM" parameter and occurrence of WM for proposed BSRWA SRAM cell with reference to previous SRAM cell (SSDF SRAM cell) is observed in Figure 8. Te histogram plot of MC simulation for SSDF SRAM cell, SSDF SRAM cell with UDVS assist circuit [20,21], SSDF SRAM cell with NBL assist circuit [15], and the proposed BSRWA SRAM cell is observed in Figure 8. Te improvement of WM for SSDF SRAM cell [14] is 15.7% (WM � 0.38 V to 0.44 V) by UDVS assist circuit [20,21] and 26.1% (WM � 0.38 V to 0.484 V) by the NBL assist circuit [15].…”

Section: Write Performance Analysis Using Wm Parametermentioning

confidence: 99%

Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell

Chokkakula

Noorbasha

2023

Active and Passive Electronic Components

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This work presents the performance and stability analysis of the proposed built-in self-read and write assist 10T SRAM (BSRWA 10T) for better performance in terms of thermal stability and fast write access, which is suitable for military and aerospace applications. The performance of the proposed SRAM cell dominates the previous SRAM cells, i.e., conventional, fully differential 10T-ST (FD 10T-ST), single stacked disturbance-free 9T-ST (SSDF 9T-ST). The proposed SRAM cell dominates the SSDF 9T-ST SRAM cell in terms of write ability. The built-in self-read and write assist structure of the memory cell also dominates the improved write ability of SSDF 9T-ST SRAM by assist circuits such as negative bit line, ultra-dynamic voltage scaling (UDVS), write assist combining negative BL, and VDD collapse. The impact of assist circuits on write performance of memory cells is observed using Monte Carlo simulation for write margin (WM) parameter. WM of SSDF 9T-ST SRAM is improved by 15% and 25% by adding UDVS assist circuit and write assist combining negative BL and VDD collapse circuit. But BSRWA SRAM cell itself can improve WM by 32% without any assist circuit. The impact of temperature variation on the performance of memory cells is observed using Monte Carlo simulation for the HSNM parameter. The deviation of HSNM for 15°C to 55°C is 14%, 5%, 4%, and 1% in conventional SRAM cell, FD 10T SRAM cell, SSDF 9T SRAM cell, and proposed BSRWA 10T SRAM cell, respectively. The proposed SRAM cell is designed at a 22 nm CMOS technology node and verified in the Synopsys Custom compiler. MC simulation results are monitored on Synopsys Cosmo-scope wave viewer.

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“…This restricts the minimal supply voltage (also known as V min ) scaling to achieve functional SRAM operation. One way to prevent such possible failures is to utilize circuit-assist techniques such as wordline underdrive (WLUD) [7] for read operations and supply voltage collapse (SVC) [8] and negative bitline (NBL) [9] during write operations. The aforementioned circuit-level assist solutions, on the other hand, necessitate a increment in power and area requirement, as well as a substantial increase in cycle time.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

Yadav

Kondekar

Awadhiya

et al. 2022

Preprint

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In this paper, a detailed evaluation of negative capacitance FinFET (NC-FinFET) based volatile static random access memory (6T-NCSRAM) is carried out by utilizing L-K equation for ferroelectric and calibrated BSIM-CMG model with 14nm conventional FinFET to form NC-FinFET. Static and dynamic behaviour of NC-FinFETs is explored and evaluated at different ferroelectric thickness. At supply voltage scaling, important SRAM performance metrics such as stability at different operation condition (hold, read and write mode) and standby leakage power were evaluated. When compared to traditional FinFET-based SRAM, 6T-NCSRAM exhibits distinct behaviour during low and high supply voltages. Moreover, the effect of wordline (WL) voltage pulse variation on 6T-NCSRAM is captured and minimum RC multiplier of 2RC is found to avoid functional failure of 6T-NCSRAM.

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SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation

Cited by 4 publications

References 14 publications

Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

Performance and Stability Analysis of Built-In Self-Read and Write Assist 10T SRAM Cell

Design and Analysis of Negative Capacitance Assisted SRAM: A Compact Model Based Study

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