17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI

Khayatzadeh, Mahmood; Saligane, Mehdi; Wang, Jingcheng; Alioto, Massimo; Blaauw, David; Sylvester, Dennis

doi:10.1109/isscc.2016.7418031

Cited by 21 publications

(20 citation statements)

References 4 publications

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“…Differently, Timing Speculation techniques correct the accessing timing faults by increasing the bitline discharging time. Khayatzadeh et al [9] proposed Razor SSRAM that distinguishes the correction of the data by comparing two successive reading samples. However, the long-time duration between the speculative and the confirm readings of Razor SSRAM limits its applications.…”

Section: A the Sram Circuitsmentioning

confidence: 99%

“…However, for all the architectural approaches, there is always a significant fraction of the cache capacity to be disabled or sacrificed for storing the additional information. In recent years, SSRAM (Timing Speculation SRAM) has been proposed, which can tolerant the timing failures when operating in the low supply voltages [9]- [11] with limited area cost. However, when SSRAM detects that a weak bit cell is accessed, it extends more cycles to further discharge the bitline to obtain the sufficient voltage swing.…”

Section: Introductionmentioning

confidence: 99%

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Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM

et al. 2019

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The probability of timing failure in SRAM accessing becomes unacceptably high at low voltages, which makes the SRAM become the bottleneck of the system performance. Recently proposed timing speculation SRAM (SSRAM) can access bit cells much earlier than the conservative time margin and detect the potential timing failures. Unfortunately, the performance benefit brought by this speculative scheme might be nullified by the extra cycles used to correct the errors. Therefore, in a cache architecture, cachelines containing bit cells with timing failure bring significant performance degradation in a low-voltage scenario. In this paper, we propose the set-associative L1 and L2 Remapping and Reuse-aware timing Speculation caches (RRS caches) based on the cross-sensing SSRAM to reduce the weak cacheline access penalties under low supply voltages. RRS caches improve the proportion of the error-free cachelines (or strong cachelines) by clustering as more as possible bit cells with timing failures into weak cachelines. In addition, RRS caches swap the frequently reused data to the error-free cachelines to further reduce the average access latency and the energy consumption by an optimized filling/replacement policy. We compared the performance, energy consumption and area overhead of RRS caches with those of state-of-the-art approaches. According to our simulation results, RRS caches improve the system performance close to that of the Perfect caches in a four-core processor with only 0.12% extra energy consumption, 4.12% extra area overhead in the L1 cache and 2.69% extra energy consumption, 5.66% extra area overhead in the L2 cache compared to the cache designs with the raw SSRAM. INDEX TERMS Cacheline remapping, low-voltage cache, near-threshold voltage, replacement policy, timing speculation SRAM.

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Section: A the Sram Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM

et al. 2019

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“…This method can also improve the SRAM performance. Khayatzadeh et al [21] propose a timing speculative SRAM that reads memory twice with dual ports in a pipelined method. In most cases, the read output is available after one clock cycle, and is then confirmed by comparison with a second sample in the next cycle.…”

Section: A Timing Speculative Srammentioning

confidence: 99%

“…The principle of Razor SRAM [21] is similar to [19]; therefore, its parameters are the same as that of [19]. In order to increase the clock frequency, it speculatively reads data through two independent ports and achieves great throughput gain at the cost of huge area overhead.…”

Section: A Timing Speculative Systemmentioning

confidence: 99%

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A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM

Yang

Guo

et al. 2018

IEEE J. Solid-State Circuits

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A double sensing with selective bitline voltage regulation (DS-SBVR) scheme is proposed to improve the throughput of ultralow-voltage static random access memory (SRAM). It senses the bitline voltage swing twice and compares two samples for confirmation. The bitline voltage is dynamically regulated by charge sharing between two sensing steps. Different from other timing speculative SRAMs, its error flag is generated much earlier; therefore, it achieves a higher reading throughput. Meanwhile, a digitized timing scheme is proposed to generate configurable timing pulses for the DS-SBVR. Compared with other timing techniques, it has a better ability to process, voltage, temperature (PVT) tracking and variance suppression. For fair comparison of performance/power/area, three different columnbased timing speculative designs are implemented in the same technology. A 28-nm test chip including 40 SRAM macros (128 × 32) is fabricated to demonstrate the scheme. Compared with the conventional design, measurements show that DS-SBVR achieves 1.45× throughput gain at 0.6-V SS corner. The figure of merit (FOM) is introduced for power, performance, and area (PPA) gain comparison. Compared with the conventional design, the FOMs of PPA gain are 1.54 and 2.33 in 128-row and 512-row memories, respectively. Compared with other timing speculative SRAMs, it achieves 1.83×-2.24× improvement.

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Memories

Veendrick

2024

Nanometer CMOS ICs

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17.3 A reconfigurable dual-port memory with error detection and correction in 28nm FDSOI

Cited by 21 publications

References 4 publications

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM

A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM

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