Background To compare the perioperative outcomes of transperitoneal laparoscopic (TLA), retroperitoneal laparoscopic (RLA), and robot-assisted transperitoneal laparoscopic (RATLA) adrenalectomy for adrenal tumors in our center. Methods Between April 2012 and February 2018, 241 minimally invasive adrenalectomies were performed. Cases were categorized based on the minimally invasive adrenalectomy technique. Demographic characteristics, perioperative information and pathological data were retrospectively collected and analyzed. Results This study included 37 TLA, 117 RLA, and 87 RATLA procedures. Any two groups had comparable age, ASA score, Charlson Comorbidity Index, and preoperative hemoglobin. The tumor size for RLA patients was 2.7 ± 1.1 cm, which was significantly smaller compared to patients who underwent TLA/RATLA (p = 0.000/0.000). Operative time was similar in any two groups, while estimated blood loss was lower for RATLA group (75.6 ± 95.6 ml) compared with the TLA group (131.1 ± 204.5 ml) (p = 0.041). Conversion to an open procedure occurred in only one (2.7%) patient in the TLA group for significant adhesion and hemorrhage. There were no significant differences between groups in terms of transfusion rate and complication rate. Length of stay was shorter for the RATLA group versus the TLA/RLA group (p = 0.000/0.029). In all groups, adrenocortical adenoma and pheochromocytoma were the most frequent histotypes. Conclusions Minimally invasive adrenalectomy is associated with expected excellent outcomes. In our study, the RATLA approach appears to provide the benefits of decreased estimated blood loss and length of stay. Robotic adrenalectomy appears to be a safe and effective alternative to conventional laparoscopic adrenalectomy.

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A double sensing with selective bitline voltage regulation (DS-SBVR) scheme is proposed to improve the throughput of ultralow-voltage static random access memory (SRAM). It senses the bitline voltage swing twice and compares two samples for confirmation. The bitline voltage is dynamically regulated by charge sharing between two sensing steps. Different from other timing speculative SRAMs, its error flag is generated much earlier; therefore, it achieves a higher reading throughput. Meanwhile, a digitized timing scheme is proposed to generate configurable timing pulses for the DS-SBVR. Compared with other timing techniques, it has a better ability to process, voltage, temperature (PVT) tracking and variance suppression. For fair comparison of performance/power/area, three different columnbased timing speculative designs are implemented in the same technology. A 28-nm test chip including 40 SRAM macros (128 × 32) is fabricated to demonstrate the scheme. Compared with the conventional design, measurements show that DS-SBVR achieves 1.45× throughput gain at 0.6-V SS corner. The figure of merit (FOM) is introduced for power, performance, and area (PPA) gain comparison. Compared with the conventional design, the FOMs of PPA gain are 1.54 and 2.33 in 128-row and 512-row memories, respectively. Compared with other timing speculative SRAMs, it achieves 1.83×-2.24× improvement.