Timing analysis taking into account interconnect process variation

Dai, Wayne Wei-Ming; Ji, Hao

doi:10.1109/iwstm.2001.933825

Cited by 18 publications

(14 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…When process variations of the BEOL layers are not fully correlated, the timing variation on a critical path is typically much smaller than that estimated using CBCs due to averaging of uncorrelated variations. 2 Our analysis (see Section III) shows that the delay variation at a CBC (with respect to the typical BEOL condition) can be much larger than the delay variation obtained from a statistical analysis. Further, we observe that the pessimism of a CBC depends on the sensitivities of critical-path delays to resistance and capacitance variations.…”

Section: Introductionmentioning

confidence: 70%

See 1 more Smart Citation

Improved signoff methodology with tightened BEOL corners

Chan

Dobre

Kahng

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

View full text Add to dashboard Cite

Abstract-To ensure functional correctness, conventional chip implementation methodology signs off the SOC design at extreme process, voltage and temperature (PVT) conditions. At the 20nm node and beyond, the back end of line (BEOL) layers have become major sources of variation, which must be accounted for by signoff at various BEOL corners. Conventional signoff methodology uses extreme BEOL corners, in which all BEOL layers are skewed to the worst-case condition (e.g., all BEOL layers have the worst parasitic capacitance). However, such a BEOL condition is very pessimistic because the probability of having all BEOL layers skew towards the worst-case condition simultaneously is extremely small. Such pessimism results in longer chip implementation schedules and poorer design quality. In this paper, we propose a signoff methodology with tightened BEOL corners to recover the pessimism incurred by the conventional BEOL corners. This approach is based on the observation that most timing-critical paths use different BEOL layers. When the variations of BEOL layers are not fully correlated, the BEOL-induced timing variation is much smaller due to averaging of random variations. Our experimental results show that by using tightened BEOL corners, we can reduce timing-violation paths by up to 100% and improve the WNS and TNS by up to 101ps and 53ns, respectively.

show abstract

Section: Introductionmentioning

confidence: 70%

“…0 otherwise (2) where Σ u,v is the entry at the u th row and v th column in Σ. γ is the correlation between z u and z v . Due to the lack of actual manufacturing data, we assume that γ is the same for different pairs of variation sources.…”

Section: B Tightened Beol Cornersmentioning

confidence: 99%

Improved signoff methodology with tightened BEOL corners

Chan

Dobre

Kahng

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

View full text Add to dashboard Cite

show abstract

“…Of these variations, within-die variation is often much greater than other variations. Some measurements of supposedly identical structures within the same die reveal variations on the order of 15% [2]. Although there are many first-order statistical analysis methods for interconnect, model accuracy may not be guarantee since first-order methods do not consider the non-linear components, especially when variations are large.…”

Section: Interconnect Variation Modelingmentioning

confidence: 99%

Deep submicron interconnect timing model with quadratic random variable analysis

Zeng

Chen

2008

Proceedings of the Conference on Design, Automation and Test in Europe

View full text Add to dashboard Cite

show abstract

“…However, Equation (9) has no closed form solution. In [10], authors expanded the equation to the first order Taylor series around t = ν using the simpler shape functions for g(t) and f (t) illustrated in Equations (1) and (2).…”

Section: Quadratic Delay Change Curve (Qdcc)mentioning

confidence: 99%

“…Statistical design methods have been proposed in the past to model the impact of process variations. However, all the existing methods deal almost exclusively with modelling delay variations of logical gates [7] or physical variations of interconnect wires [8,9]. This paper deals with a method of analytically analyzing statistical behavior * Dr. Chen is also with the Department of Electrical and Computer Engineering, Colorado State University of multiple coupled interconnects with an uncertain signal arrival time at each interconnect input.…”

Section: Introductionmentioning

confidence: 99%