This paper considers simultaneous gate and wire sizing for general VUI circuits under the E[more delay model. JVepresent a fast and met algorithm which can minimize total area subject to mmimurn delay bound. The algorithm can be easily modl~ed to givẽ wct algorithms for optimizing several other objectives (e.g. minimizing maximum delay or minimizing total area subject to arrival time specl~cations at all inputs and outputs). No previous algorithm for simultaneous gate and wire sizing can guarantee met solutions for general circuits. Our algorithm is an iterative one with a guarantee on convergence to global Oph.malsolutions. It is based on hgransian relmtion and "one-gatdwire-at-a-time" local optimi~tions, and is mtremely economical and fast. For example, we can optimize a circuit with 27,648 gates and wires in about 36 minutes using under 23 MB metnory on an IBM RS/6000 worhtation.

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In this paper, we consider non-uniform wire-sizing under the Elmore delay model. Given a wire s e gment of length L, let fx be the width of the wire a t p osition x, 0 x L .It was shown in 2, 5 that the optimal wire-sizing function which minimizes delay is an exponential tapering function fx = ae ,bx , where a 0 and b 0 are c onstants.Unfortunately, 2, 5 did not consider fringing capacitance which is at least comparable in size to area c apacitance i n deep submircon designs. As a result, exponential tapering is no longer the optimal strategy. In this paper, we show that the optimal wire-sizing function, taking fringing capaci-,n n,1 n! x n is the Lambert's W function, cf and c0 are the respective fringing capacitance and area c apacitance of wire p er unit square, a 0 and b 0 are c onstants.The optimal wire-sizing function degenerates into an exponential tapering function as cf = 0 , and degenerates into a square-root tapering function fx = p b , ax; where a 0 and b 0 a s c f ! 1 . Our experimental results show that the optimal wire-sizing function can signi cantly reduce the interconnection delay of exponentially tapered wires. In the case where lower and upper bounds on the wire widths are given, the optimal wire-sizing function is a truncated version of the above function. Finally, our optimal wire-sizing function can be iteratively applied to optimally size all the wire segments in a routing tree for objectives such as minimizing weighted sink delay, minimizing maximum sink delay, or minimizing area subject to delay bounds at the sinks.

Delay, power, skew, area, and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buers in clock trees. Our algorithm, based o n L agrangian relaxation method, can optimally minimize delay, power, and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast, and accurate; for example, our algorithm can solve a 6201-wire-segment clock-tree p r oblem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation.

Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] a noiseaware repeater insertion technique has also been proposed recently. Recognizing the conservatism of these delay and noise models, we propose a moment-matching based technique to interconnect optimization that allows for much higher accuracy while preserving the hierarchical nature of Elmore-delay-based techniques. We also present a novel approach to noise computation that accurately captures the effect of several attackers in linear time with respect to the number of attackers and wire segments. Our practical experiments with industrial nets indicate that the corresponding reduction in error afforded by these more accurate models justifies this increase in runtime for aggressive designs which is our targeted domain. Our algorithm yields delay and noise estimates within 5% of circuit simulation results.