Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation

Chen, Chung-Ping; Chang, Yao‐Wen; Wong, D.F.

doi:10.1145/240518.240596

Cited by 32 publications

(38 citation statements)

References 19 publications

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“…Multiplying (1) by , we have , which can be rewritten as as by (2). Since is positive definite and is of full rank, is invertible.…”

Section: Solving Convex Quadratic Programs By Active Set Methodsmentioning

confidence: 99%

“…We can solve this problem by the Lagrangian relaxation technique as in [2]. Basically, the program above is reduced to a sequence of programs of the following form: minimize subject to for where is the Lagrange multiplier.…”

Section: ) Area Minimization With Bounded Delaymentioning

confidence: 99%

“…Almost all the previous approaches to interconnect delay optimization that use wire sizing divide a wire into small fixed-length segments and optimize the width of each segment iteratively. Some examples are [4], [9], [13], [26], and [29] for wire sizing alone, [2], [8], [12], and [25] for simultaneous buffer sizing and wire sizing, and [22] for simultaneous buffer insertion, buffer sizing, and wire sizing. See [11] for a comprehensive survey.…”

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confidence: 99%

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A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

Chu

Wong

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore some special properties of our problem and derive an optimal and very efficient algorithm modified active set method (MASM) to solve the resulting program. Given m buffers and a set of n discrete choices of wire width, the running time of our algorithm is O(mn 2 ) and is independent of the wire length in practice. For example, an instance of 100 buffers and 100 choices of wire width can be solved in 0.92 s. In addition, we extend MASM to consider simultaneous buffer insertion, buffer sizing, and wire sizing. The resulting algorithm MASM-BS is again optimal and very efficient. For example, with six choices of buffer size and 10 choices of wire width, the optimal solution for a 15 000 m long wire can be found in 0.05 s. Besides, our formulation is so versatile that it is easy to consider other objectives like wire area or power dissipation, or to add constraints to the solution. Also, wire capacitance lookup tables, or very general wire capacitance models which can capture area capacitance, fringing capacitance, coupling capacitance, etc. can be used.

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“…Multiplying (1) by , we have , which can be rewritten as as by (2). Since is positive definite and is of full rank, is invertible.…”

Section: Solving Convex Quadratic Programs By Active Set Methodsmentioning

confidence: 99%

Section: ) Area Minimization With Bounded Delaymentioning

confidence: 99%

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confidence: 99%

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A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

Chu

Wong

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Contrasting the initial unbuffered clock a tree, a most extreme of 27x delay change is attained by buffer insertion and sizing. Chen et al [23] plan the clock area/delay/power minimization issue for buffered clock trees as a geometric programming issue and tackle it utilizing Lagrangian Relaxation techniques. The current clock tree optimization lives up to expectations, either dynamicprogramming-based or numerical programming-based, either just uses one or two accessible improvement systems, i.e., buffer insertion, buffer sizing and wire sizing, or think as of them in independent stages.…”

Section: Literature Surveymentioning

confidence: 99%

Minimizing Skew and Delay with Buffer Resizing and Relocation during Clock Tree Synthesis

Punia¹,

Rouble²,

Shukla³

et al. 2014

IJCA

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Rapidly increasing design complexity due to small size and higher speed, results in the problem of clock skew and insertion delay. These are the two important parameters which should be considered for successful completion of the design. In this work, a method for minimizing clock skew by buffer insertion and resize is proposed. Clock skew will be minimized during post-CTS timing analysis after placement of standard cells during physical implementation of the design. Also, buffer relocation method is used for minimizing the delay of the cells. Simulations were carried out on EDA tools and results show that overall skew is improved by 23.95% and delay is improved by 19.50%.

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“…The board routes some pins of the FPGA (ML 505), Routed to Clock IO, to small connectors. The 50-ohm Coaxial cables to clock the FPGA and to analyze its output (Aloisio et al, 2010;Chen et al, 1996;ITRS, 2003;Data, 2006). In addition to this, Clock generator having a random jitter and is very small approximately 4.5 ps directed to the board.…”

Section: Models For Stochastic Simulationmentioning

confidence: 99%

Optimization of Clock Tree Synthesis Under Stochastic Process Variation Modeling for Multi-Fpga Systems

Sampath¹

2013

American Journal of Applied Sciences

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In this age of scientific computing, the experiment models and evaluation is a commonly employed rendition of the simulation methods. In addition to the optimality, the methods which depict underlying uncertainty in process variation. It is accomplished by adjusting number of samples on delay and wire width. Here addresses the thermal profile, if temperature gradually increases, also reduce worst case clock skew under thermal variation. Under the SSTA analysis the mean delay is 6.2 to 5.2% and standard deviation from 7.5 to 7.6% is reduced. Therefore the overall performance measure in storage and the run time is very low. Extensive simulation studies show that of how does one accurately and efficiently postprocess stochastic simulation fields and how does one effectively and succinctly convey the results.

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Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation

Cited by 32 publications

References 19 publications

A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

Minimizing Skew and Delay with Buffer Resizing and Relocation during Clock Tree Synthesis

Optimization of Clock Tree Synthesis Under Stochastic Process Variation Modeling for Multi-Fpga Systems

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