We explore a novel phenomenon of focused ion beam (FIB) induced bending of carbon nanopillars or cantilever structures. The bending occurs towards the ion beam during scanning. The explanation of this bending has been sought on the basis of a model which considers temperature rise and gradients caused by the impinging ion beam. The process is controllable and reversible, which makes it highly suitable for in situ manipulation to make desired 3D shapes by the piecewise bending of the nanopillars and cantilever structures during their fabrication using electron beam or FIB chemical vapor deposition (EB-CVD or FIB-CVD). Its usefulness in the fabrication of nanosize mechanical components has been demonstrated by making a branch structure from a single cantilever.

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In this work, we studied cobalt nitride (Co-N) thin films deposited using a dc magnetron sputtering method at a substrate temperature (T s ) of 523 K. We find that independent of the reactive gas flow (R N 2 ) used during sputtering, the phases of Co-N formed at this temperature seems to be identical having N at.% ∼5. This is contrary to Co-N phases formed at lower T s . For T s ∼300 K, an evolution of Co-N phases starting from Co(N)→Co 4 N→Co 3 N→CoN can be seen as R N 2 increases to 100%, whereas when the substrate temperature increases to 523 K, the phase formed is a mixture of Co and Co 4 N, independent of the R N 2 used during sputtering. We used x-ray diffraction (XRD) to probe long range ordering, x-ray absorption spectroscopy (XAS) at Co absorption edge for the local structure, Magneto-optical Kerr e ffect (MOKE) and polarized neutron reflectivity (PNR) to measure the magnetization of samples. Quantification of N at.% was done using secondary ion mass spectroscopy (SIMS). Measurements suggest that the magnetic moment of Co-N samples deposited at 523 K is slightly higher than the bulk Co moment and does not get affected with the R N 2 used for reactive sputtering. Our results provide an important insight about the phase formation of Co-N thin films which is discussed in this work.

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To meet the increasing demands for higher performance and low-power consumption in present and future Systems-on-Chips (SoCs) require a large amount of on-die/embedded memory. In Deep-Sub-Micron (DSM) technology, it is coming as challenges, e.g., leakage power, performance, data retentation, and stability issues. In this work, we have proposed a novel low-stress SRAM cell, called as IP3 SRAM bit-cell, as an integrated cell. It has a separate write sub-cell and read sub-cell, where the write sub-cell has dual role of data write and data hold. The data read sub-cell is proposed as a pMOS gated ground scheme to further reduce the read power by lowering the gate and subthreshold leakage currents. The drowsy voltage is applied to the cell when the memory is in the standby mode. Further, it utilizes the full-supply body biasing scheme while the memory is in the standby mode, to further reduce the subthreshold leakage current to reduce the overall standby power. To the best of our knowledge, this low-stress memory cell has been proposed for the first time. The proposed IP3 SRAM Cell has a significant write and read power reduction as compared to the conventional 6 T and PP SRAM cells and overall improved read stability and write ability performances. The proposed design is being simulated at VDD = 0.8 V and 0.7 V and an analysis is presented here for 0.8 V to adhere previously reported works. The other design parameters are taken from the CMOS technology available on 45 nm with tOX = 2.4 nm, Vthn = 0.224 V, and Vthp = 0.24 V at T = 27?C