Characterization of a Novel Low-Power SRAM Bit-Cell Structure at Deep Sub-Micron CMOS Technology for Multimedia Applications

Singh, R. K.; Pattanaik, Manisha; Shukla, Neeraj Kr.

doi:10.4236/cs.2012.31004

Cited by 11 publications

(15 citation statements)

References 9 publications

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“…In [14], an IP3 SRAM Bit-Cell structure has been presented by Rakesh Kumar Singh et al which uses drowsy scheme and pMOS stacking with ground. This cell reduces the power consumption (active, leakage, standby) with the small area penalty.…”

Section: Proposed Mtip3 Sram Bit-cellmentioning

confidence: 99%

Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants

Yadav¹,

Shukla²,

Bhatnagar³

et al. 2015

IJCA

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Bio-Implantable Microsystems such as the cardiac pacemaker, retinal and neural implant provides substitute for a missing biological part, support an impaired biological structure or even upgrade the existing biological system. These microsystems require ultra-low power miniature integrated circuit technology for long term reliable operation. For energy constraint applications like the implantable devices, the performance requirement are secondary factors while energy efficiency, low power, high density and high robustness are of primary concern. For low power operation, scaling the supply voltage into sub-threshold region is possible and is an effective technique for power reduction. Implantable devices require minimum energy consumption and prolonged battery lifetime. So these systems demand low leakage currents without sacrificing much on performance. In this work a new 9T MTIP3 SRAM Bit-Cell is proposed at 45nm CMOS technology using multi-threshold (MTCMOS) design technique. The static power saving in MTIP3 is 99.83% as compared to conventional 6T and 23.82% as compared to IP3 at VDD=0.8V. The dynamic power saving of read1 in MTIP3 is 86.37% as compared to 6T. The dynamic power saving of write1 in MTIP3 is 66.23% as compared to IP3. The access time of MTIP3 is 16.94% less than 6T. The energy saving during hold mode in MTIP3 is 99.5% as compared to 6T. Static Noise Margins are improved by 2.07% compared to IP3 at VDD =0.7V.

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Section: Proposed Mtip3 Sram Bit-cellmentioning

confidence: 99%

Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants

Yadav¹,

Shukla²,

Bhatnagar³

et al. 2015

IJCA

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“…IP3 [7] SRAM bit-cell is also known as low stress SRAM cell. It has 2 separate subcell for write and read, where write sub cell has dual role of data write and data hold.…”

Section: Ip3 Cellmentioning

confidence: 99%

A Novel Optimal 2-D Layout for Cache Memory at 45nm CMOS Technology

Komal¹,

Saxena²,

Chaturvedi³

et al. 2015

IJAST

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“…In [16], a novel low-stress SRAM cell has been proposed, named as IP3 SRAM bit-cell, as an integrated cell. It has a separate write sub-cell and read sub-cell, where the write sub-cell has dual role of data write and data hold.…”

Section: Related Work-a Reviewmentioning

confidence: 99%

Analysis and Simulation of Subthreshold Leakage Current Reduction in IP3 SRAM Bit-Cell at 45nm CMOS Technology for Multimedia Applications

Pattanaik¹,

Shukla²,

Singh³

2011

IJCTE

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Abstract-Leakage currents in deep sub-micrometer regimes is becoming a significant contributor to power dissipation in CMOS digital circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Therefore, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power consumption, especially for battery powered and portable low-power applications. In this work we have performed an analysis and circuit level simulation at Deep Sub-Micron (DSM) Complementary Metal Oxide Semiconductor (CMOS) technology, pdk45nm. The simulation has been performed on the existing Static Random Access Memory (SRAM) cell structures, e.g., the conventional 6T, PP, P4, P3, and IP3 cells, to calculate the Subthreshold and standby leakage powers at V DD =0.7V and 0.8 V. It is found that the IP3 Cell has minimum subthreshold leakage current (at standby mode), i.e., 90%, 95%, 50%, and 51% as compared to the 6T, PP, P4, and P3 cells, respectively at no performance and stability loss with a small area penalty. The standby leakage power is better in P4, and P3 cells by 59%, and 23% to IP3 cell but at the cost of degraded cells' data retentation and stability. The standby leakage power in IP3 is reduced by 36% and 52% in comparison with 6T and PP cell with improved cell stability and performance. The simulation has been carried out on t ox = 2.4nm, V thn = 0.22 V, V thp = 0.224 V, V DD =0.8 V, 0.7 V, T= 27 °C.

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Characterization of a Novel Low-Power SRAM Bit-Cell Structure at Deep Sub-Micron CMOS Technology for Multimedia Applications

Cited by 11 publications

References 9 publications

Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants

Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants

A Novel Optimal 2-D Layout for Cache Memory at 45nm CMOS Technology

Analysis and Simulation of Subthreshold Leakage Current Reduction in IP3 SRAM Bit-Cell at 45nm CMOS Technology for Multimedia Applications

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