A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing

Abstract

Abstract-In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore some special properties of our problem and derive an optimal and very efficient algorithm modified active set method (MASM) to solve the resulting program. Given m buffers and a set of n discrete choices of wire width, the running time of our algorithm is O(mn 2 ) and is independent of the wire length in practice. For example, an instance of 100 buffers and 100 choices of wire width can be solved in 0.92 s. In addition, we extend MASM to consider simultaneous buffer insertion, buffer sizing, and wire sizing. The resulting algorithm MASM-BS is again optimal and very efficient. For example, with six choices of buffer size and 10 choices of wire width, the optimal solution for a 15 000 m long wire can be found in 0.05 s. Besides, our formulation is so versatile that it is easy to consider other objectives like wire area or power dissipation, or to add constraints to the solution. Also, wire capacitance lookup tables, or very general wire capacitance models which can capture area capacitance, fringing capacitance, coupling capacitance, etc. can be used.

Buffer Insertion for Delay Minimization using An Improved PSO Algorithm

“…Inputs of the PSO algorithm for this section are listed in table (8,9). To compare between the PSO results and the …”

“…Also we can change the size of buffers as well as the lengths and widths of segments in order to minimize the delay from source to sink. In previous years, several closed form optimal solutions for interconnect optimization problems have been given [1,4,5,6,7,8,9,10]. In these studies, the delay minimization problem of on-chip interconnect wire is considered by simultaneous buffer insertion/sizing, and wire sizing.…”

Performance Optimization of Nonlinear VLSI Interconnect Circuit using Schmitt Trigger

“…Many such buffers along an interconnect can thus contribute towards overall delay to signal propagation. Also, buffer switching contributes to power dissipation [5].…”

A fast algorithm for optimal buffer insertion

“…Vertex is the source vertex [2], [4], [7], [8], [9], [14], [15] for each edge , possible buffer position , and buffer library , find a candidate for that maximizes . An example of the buffer insertion problem is shown in Fig.…”

“…For buffer insertion on a single line allowing continuous buffer positions and continuous buffer sizes, Dhar and Franklin [6] proposed a closed form solution, and Chu and Wong [4] Manuscript received February 5, 2004;revised June 18, 2004. This work was supported in part by the National Science Foundation under Grant CCR-0098329, Grant CCR-0113668, Grant EIA-0223785, and ATP Grant 512-0266-2001, and in part by a fellowship from Applied Materials.…”